最小轉換差動信號傳送器

Abstract

本篇論文是設計一個應用於高速串列數位影像傳輸介面，使用最小轉換差動信號的傳送器。整個傳送器電路包含多相位之鎖相迴路，十對一多工器和輸出驅動器。 多相位之鎖相迴路的輸入頻率為25∼165MHz，提供10個相位且輸出頻率同樣為25∼165MHz的時脈，所包含的電路有相位／頻率偵測器、充電泵浦、迴路濾波器、十個相位的壓控振盪器。多相位鎖相迴路可應用於解析度由VGA（640×480）到UXGA（1600×1200）平面顯示器的傳輸介面，使用5級差動式多相位壓控振盪器產生10個相位精確且平均分布於一個週期內的時脈，提供十對一多工器將一組並列資料轉換成串列輸出。最後再透過一輸出驅動器，增加電流驅動能力，完成整個傳送器的設計。 此傳送器採用 1P4M CMOS製程技術實現，電壓電源為3.3V。當輸入時脈為25MHz時，量測結果顯示鎖相迴路輸出訊號的方均根抖動和峰值抖動分別為15.66ps和110ps，消耗功率為20mW。

This thesis describes the design of a transmitter for a high-speed serial digital display interface that uses transition minimized differential signaling (TMDS) to send data to the monitor. The transmitter consists of a multi-phase phase-locked loop (PLL), a 10-to-1 multiplexer and a data driver. The multi-phase PLL with input frequency range from 25MHz to 165MHz can offer ten-phase clock output that has the same frequency with the input signal. It is composed of a phase-frequency detector (PFD), a charge pump (CP), a loop filter and a ten-phase voltage-controlled oscillator (VCO). The PLL can support several different video display modes from VGA (640×480) to UXGA (1600×1200). Ten different clock phases tapped from a five-stage differential ring oscillator to determine the bit time. They also control the transmitter multiplexing. Finally, the data driver outputs serial data steam. The transmitter is implemented in a 1P4M CMOS process and the supply voltage is 3.3V. The measured rms and peak-to-peak jitters of the 25MHz output clock of the PLL are 15.66ps and 110ps, respectively, and power consumption is 20 mW.