最小轉換差動訊號接收器

Abstract

隨著 CMOS 製程技術的發展，以及處理器運算能力的快速提昇，提示著用以傳輸資訊的寬頻資料連結越來越顯得需要。在許多的應用中，比如說電腦內部、電腦與電腦間和電腦與週邊間的介面，這樣的連結通常是一個很重要的部分。為了克服在資料傳輸過程中由各種雜訊源所導致的訊號完整性問題，接收器在整個高速連結效能的表現中扮演了一個重要的角色。本篇論文描述以TMDS 傳送方式為基礎的介面之追蹤式資料回復系統設計。接收器試圖在接收端回復在 Gb/s 等級速率的傳輸資料。 為了正確地將接收到的信號回復成二進制的數位資料，一個具有數位式迴授控制迴路的系統架構被提出來。利用三倍超頻取樣的技巧，這個追蹤式的資料回復系統可以在模擬結果中正確地回復 1.65 Gb/s 的傳輸資料。這個系統避免了在兩倍取樣的系統中會遭遇到的亞穩態問題，並保持了閉迴路的相位校正特性。此接收器亦擁有簡單資料選取邏輯電路與數位相移機制兩個優點，因此可減低硬體設計複雜度與增加對雜訊抵抗的能力。兩組多相位產生器被採用在此接收器的實現上。相位鎖定迴路由於其具有頻率合成的特性故被採用為參考相位產生器，而延遲鎖定迴路基於其較佳的不累積抖動特性，它被採用作取樣相位產生器。此接收器最後將對回復信號作解多工處理以轉成四個並行資料輸出。

The scaling of CMOS process technologies and the increasing computational capability of processors, indicate that high bandwidth links to communicate the information are needed. Such high speed links are often important parts of inner- computer, computer-to-computer or computer-to-peripheral interfaces. To overcome the signal integrity problems induced by various noise sources during data transmission period, the receiver design plays an important role in the overall performance of high speed links. This thesis describes the design of a tracking data recovery receiver for the TMDS based interface. The receiver tries to recover the transmitted data at the receiving end with the data rate at Gb/s range. To recover the received signal back to digital binary data correctly, a system architecture with a digital feedback control loop is proposed. With the 3 times oversampling technique, the signal transmitted in a mesochronous system could be recovered correctly by the tracking data recovery system with the data rate at 1.65 Gb/s in the simulation result. The system prevents the metastability problem in 2 times oversampling tracking systems, keeping the closed loop phase calibration mechanism. The receiver also has the advantages of simple data selection logic and digital phase shifting mechanism, thus simplifying the hardware design and improving noise immunity. Two multiple phase generators are adopted in the tracking receiver system. The PLL is used as reference clock generator due to its ability to synthesize higher frequency outputs. And the DLL is taken as sampling clock generator because of its better non-accumulated jitter property. Finally, the input data stream could be demultiplexed by this system to be four parallel data channels.