高速輸出輸入介面之電路設計

Abstract

摘要 近年來由於處理器運算速度越來越快，單位時間處理的資料量也日益增多，因此在電腦週邊設備資料的傳輸，及各式積體電路產品應用，這些都必須靠一個能大量傳送和接收資料量的介面電路來完成。在數十公里，甚至數百公里以上的長距離傳輸方面，可以利用光纖作為傳輸的工具，可是在幾十公尺甚至PCB上各晶片匯排流資料的傳輸，光纖傳輸就不切實際，因此必須靠纜線或是PCB上的傳輸線來收發資料。而若要達到高速且低功率的要求，則多採用差動低電壓模式來傳送訊號。 本論文研究的方向主要分為兩部份，第一部份是低壓差動訊號（LVDS）收發機的電路設計，它是利用0.25um CMOS的製程來實現，且操作在2.5V的電壓下，收發速度能達到超過1 Giga-bit/s的要求。 論文的第二部份則是正向射極耦合邏輯（PECL）發射機電路設計，它是利用操作在3.3V 0.35um CMOS 的製程來實現，與ECL 100K的邏輯電路相容，該電路之高電壓準位為2.35,低電壓準位為1.6V，其傳送速度能達到1 Giga-bit/s以上。 在這篇論文提到的兩種I/O介面的電路設計，都是點對點串列傳輸的形式，同時因為低功率及產生的雜訊少，具有廣泛之用途。

ABSTRACT In recent year, the operation speed of processor becomes faster and faster, and could deal with huger data in unit time. Therefore, it needs a giga-bit transceiver interface circuit for the transmission between peripheral equipments of computer, and application at kinds of manufactures in life. Optical fiber transmission is adopted for long distance such as several miles, but it is impractical for bus transmission on PCB or local communication such as several meters long. The cable or transmission line on PCB is applied. For taking high speed and low power into account, the transceiver use differential low voltage to transmit signal. The research of this thesis separate two sections. First the low voltage differential signal (LVDS) transceiver is introduced. It is implemented by 2.5V 0.25um CMOS process, and the data rate would exceed one gigabit per second. The second section, positive emitter couple logic (PECL) transmitter is introduced. It operates under 3.3V power supply, and is implemented by 0.35um CMOS process. The transmission data rate could also exceed one gigabit per second. The proposed I/O interface circuits are both point-to-point serial port transmission. Because of low power consumption and low noise, they are widely used for high data rate communication application.