新式金氧半場效電晶體之閘極與源/汲極工程研究

Abstract

在本論文中，我們針對金氧半場效電晶體之閘極與源/汲極部分進行研究，涵蓋內容包括基本的複晶矽閘極蝕刻程式建立，自我對準T型閘極電晶體研製，氮化鈦金屬閘極電晶體之熱穩定性，具副閘極(sub-gate)的絕緣層上矽(SOI)電晶體及具副閘極、Fin結構之SOI電晶體的特性研究及利用超淺鍺摻雜改善短通道效應等。 我們成功建立一蝕刻複晶矽薄膜程式，適用於不同摻雜種類及濃度的蝕刻，並具有高蝕刻率、均勻性及良好側圖控制(profile control)等。經臨界電壓、崩潰電荷及電荷泵浦(charge pumping)分析佐證可知，此程式對天線元件僅有少量的損傷，可應用於深次微米元件複晶矽閘極製作。 其次，我們成功研製出一新式可同時形成自我對準T型閘極與空氣邊壁子(air spacer)的電晶體結構，簡稱STAIR(self-aligned T-shaped gate and air spacer)。除可有效降低閘極電阻外，空氣邊壁子的形成對降低寄生電容亦深具潛力。然而製程引起的閘極漏電流將損壞氧化層品質。為此，我們引入氮化矽邊壁子大幅降低閘極漏電流，並降低橋接的機率。此結構不僅簡單且與傳統自我對準金屬矽化物(salicide)製程相容，應用於高速元件或高頻電路中將深具潛力。 為解決複晶矽空乏效應對元件特性退化的影響，似乎無法避免回歸金屬閘極結構，然而金屬閘極本身亦存在許多問題。我們研究快速退火溫度對氮化鈦為金屬閘極CMOS元件之熱穩定性影響。電容-電壓結果顯示，氧化層厚度及平帶電壓均受退火溫度影響，尤以p-通道元件為甚。此外，在p型電晶體次臨界電流特性中觀察到隆起(hump)的現象，經分析可知與隔絕區邊緣的漏電路徑有關。在n型電晶體方面，退火溫度提升與通道長度縮減易引起氮化鈦膜團塊化現象，因而破壞氧化層品質導致閘極漏電流。 我們提出一新蕭特基源/汲極SOI場效電晶體結構，係利用一金屬副閘極沈積於氧化層上，偏壓於副閘極上在通道層感應出汲極(field-induced-drain)。依據偏壓模式的不同，同一元件可操作於n或p通道模式且有極佳的開關電流比；對n通道約為107，對p通道可高達108。更重要的一點，電晶體的關閉電流在副閘極適當偏壓下顯得微不足道。此外，在n通道操作時觀察到負微分電導(negative differential conductance, NDC)的現象，成因與大量熱電子在氧化層中被捕捉有關。 其次，沿用具副閘極之蕭特基源/汲極結構製作Fin SOI場效電晶體，完成90 nm通道長度及50 nm Fin寬度的操作，亦可操作於n或p通道模式下且開關電流比高達108。長通道元件中次臨界擺幅隨Fin寬度縮減而下降接近60 mV/dec.的理想值。此外，電晶體的導通電流隨副閘極偏壓的增加而明顯上升，主要受到源極端能障變低所致，但副閘極偏壓增加卻也造成副閘極感應能障下降，而加速臨界電壓下跌；關閉電流在副閘極適當偏壓下亦不明顯。p通道操作時，矽化鉑較矽化鈷有較低的蕭特基能障利於電洞穿遂，因此矽化鉑較矽化鈷有較高的導通電流。 最後，利用低能量與低劑量大角度之鍺離子佈植源/汲極區域，臨界電壓與DIBL（drain-induced barrier lowering）等短通道效應明顯的被抑制，同時有不錯接面漏電流。然而有較差的熱載子免疫力。

In this thesis we have investigated several novel methods for gate and source/drain engineering of MOSFETs. These methods include the design of a universal recipe for etching polysilicon layer with different doping types, the fabrication of a novel T-shaped-gate transistor with air spacer. In addition, we have also studied the thermal stability of metal-gated CMOS transistors. Finally, we have also fabricated novel ambipolar Schottky S/D SOI MOSFETs with field-induced drain, and Schottky FinFETs with field-induced source/drain extensions. In closing, the effects of shallow germanium halo implant on the characteristics of nMOSFETs are also investigated. To start with, a universal etch recipe which is capable of anisotropically etching polysilicon gate layers of different doping types and concentrations with high etching rate, superior uniformity and good profile control is successfully demonstrated using a commercial TCP etcher. Only minor plasma induced damage is detected as monitored by the antenna devices, indicating that it is feasible for deep sub-micron CMOS process integration. Next, a novel transistor with self-aligned T-shaped gate and air spacer has been successfully demonstrated, which we dubbed STAIR. The STAIR transistors depict reduced gate resistance, and inherently reduced parasitic capacitance. However, in the original process flow, the gate oxide is exposed during the required long BOE treatment, resulting in large gate leakage. To alleviate this problem, an improved process with the protection of thin nitride layer at the sidewall of poly-Si gate is proposed and proved to effectively reduce the gate leakage as well as bridging probability. The refined process is robust and compatible with salicide processing, which is suitable for future high-speed device and high frequency circuit applications. To solve the device performance degradation caused by Poly-Si gate depletion effect, the use of metal gate seems to be inevitable. However, metal gate technologies possess many issues. In this thesis, we have investigated the thermal stability of CMOS transistors with TiN metal gate. It is found that oxide thickness and flat-band voltage are both affected by rapid thermal annealing temperature, especially for p-channel devices. Moreover, a hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to occur during high-temperature RTA step as gate length becomes smaller, thus, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel devices. In this thesis, we have also proposed and fabricated a novel Schottky-barrier source/drain (S/D) silicon-on-insulator (SOI) MOSFET featuring field-induced-drain (FID) structure, which is controlled by a metal field plate (or sub-gate) overlying the passivation oxide. Depending on the bias polarity, ambipolar operation and excellent on/off current ratio is achieved on the unique device. More importantly, the offset leakage current becomes negligible with the proper sub-gate bias. In addition, the negative conduction (NDC) phenomenon is observed in n-channel operation, which is ascribed to the hot electron trapping during device characterization. Next, we have also applied the FID concept to fabricate a novel Schottky-barrier (SB) FinFET with field induced source/drain extensions. We have successfully demonstrated SB-FinFET with gate length of 90 nm and 50 nm fin width. The new device exhibits superior ambipolar characteristics and high on/off current ratio of 108. In long channel devices, subthreshold slope (SS) approaches the ideal value of 60 mV/dec for narrow-fin-width devices. The output current increases with increasing sub-gate bias, which is presumably due to the tunnel barrier lowering at the source side. The off-state leakage current becomes negligible with the proper sub-gate bias. However, it was found that threshold roll-off is magnified with increasing sub-gate bias, which is probably due to sub gate induced barrier lowering. The silicide material, PtSi with its lower barrier height for holes further enhances the output current, compared with using CoSi2 in p-channel operations. Finally, we have investigated the use of shallow germanium halo doping on improving the short channel effects of deep-submicron n-channel MOSFETs. We demonstrate that the incorporation of such a shallow Ge halo implant is effective in improving threshold voltage roll-off and drain-induced barrier lowering, while maintaining a low junction leakage. However, hot-carrier degradation dose not seem to be improved by Ge halo implant.