新穎堆疊矽/鍺T型閘極複晶矽薄膜電晶體

Abstract

多晶矽薄膜電晶體擁有高載子遷移率目前被廣泛地運用在主動矩陣式液晶顯示器開關元件，然而，在汲極端產生的強電場會造成嚴重漏電流和元件不穩地性，將會阻礙多晶矽薄膜電晶體在高效能積體電路的應用。造成漏電的主要因素是由於在汲極端附近的強電場經由顆粒邊界的受限載子引起場發射而使漏電上升。 在本論文中，我們針對多晶矽薄膜電晶體提出新的製程方法，此製程簡單無需額外的光罩，或是離子佈植步驟，即可形成堆疊矽/鍺T型閘極元件，期可達到抑制電場效果。利用模擬軟體來分析證明，藉由T型閘極可有效降低汲極端附近的電場。 我們對於堆疊矽/鍺T型閘極複晶矽薄膜電晶體，探討其元件特性，包括傳輸性能、開/關電流比、漏電強度、輸出性能，以及熱載子可靠度分析。由結果顯示，堆疊矽/鍺T型閘極複晶矽薄膜電晶體，可使漏電流降低，並提升開/關電流比，此外Kink效應及熱載子可靠度也明顯優於傳統元件。

Polycrystalline silicon thin-film transistors (poly-Si TFTs) are commanding increasing interest in the field of active matrix addressed flat panel display because the higher carrier mobility in this material compared with a-Si:H TFTs, which makes it suitable for the integration of addressing circuits in the displays. However, a large off-state leakage current and device instability caused by a high electric field near the drain junction are obstacles to the high-performance circuit application of the poly-Si TFTs. The dominant mechanism of the high off-state leakage current is known to be the field emission via grain boundary traps due to a high electric field in the drain depletion region. In this thesis, we have proposed a new fabrication method of poly-Si TFT without a troublesome ion implantation or any additional mask. This device employs the stacked Si/Ge T-Gate to suppress the electric field. It was verified by the devices simulator that the electric field is reduced near the drain junction by the T-Gate structure. We have investigated the electrical characterizations of the Si/Ge T-gate TFTs including the transfer characteristics, On/Off current ratio, off -state leakage, output characteristics and hot carrier stress. The results show that the Si/Ge T-Gate TFT give low off-state leakage, the suppress of floating body effect, good On/Off current ratio and better hot carrier reliability.