先進深次微米金氧半導體場效電晶體基極與源/汲極工程之研究

Abstract

摘要 在本論文中,我們針對深次微米元件的基極與源/汲極部份進行研究,涵蓋的內容包括淺溝渠隔離技術,銦所形成超陡峭通道雜質分布元件,短通道效應以及有效通道長度量測等. 研究中發現,以提高場氧化層所製成淺溝渠絕緣結構有效抑制由於電場集中於淺溝渠角落造成的不正常導通.當通道寬度小於 0.3 mm 亦未出現反向窄寬度效應,此結構提供較寬的製程範圍與較佳的電性特性. 研究發現,銦超陡峭通道元件相較於傳統硼通道元件,有較高線性區轉移電導以及較低的飽和驅動電流.此外,銦掺雜超陡峭通道元件在DIBL, Ion-Ioff電流比率以及電晶體崩潰有較佳的特性,並且,我們發現增加銦原子離子布植能量,元件有較佳的轉移電導及熱載子免疫力. 利用高能量,大角度砷離子佈植提供較佳的PMOS短通道效應,研究發現, 砷離子柨植穿越多晶矽層影響基材雜質分佈並形成平坦的臨界電壓短通道效應, 論文充份探討此現象造成電性特性的影響. 最後我們提出一個新潁的有效通道長度量測方法,以改善的電容電壓 (C-V)量測,相較於傳統電流電壓法(I-V)及平移比例法(shift and ratio)得到一穩定的有效通道長度,寄生電容(CGD)亦可藉由此方法求得.

Abstract In this study, we investigated the substrate and source/drain engineering of deep sub-micron MOSFET’s including shallow-trench isolation (STI) with raised-field-oxide structure, the effects of super-steep-retrograde (SSR) indium channel, the optimization of short channel effect with arsenic halo implant through polysilicon gate and a modified capacitance-voltage method used for Leff extraction. A novel shallow-trench isolation (STI) structure to suppress the corner metal-oxide semiconductor field-effect transistor (MOSFET) inherent to trench isolation. With this raised-field-oxide structure, the anomalous subthreshold conduction of the shallow-trench isolated MOSFETs due to electric-field crowding at the active edge has been successfully eliminated. No inverse-narrow-width effect is observed as the device width has been scaled down to 0.3 mm. The raised-field-oxide structure provides a larger process margin for planarization, and good device characteristics were achieved by this novel STI structure. A comprehensive study on the effects of indium channel implant energy on transistor characteristics including carrier mobility, drain current, drain induce barrier lowering (DIBL), device breakdown, junction leakage, impact ionization rate and hot-carrier degradation were performed on 0.1 mm NMOS devices. It was found that devices with super-steep-retrograde (SSR) indium channel profile shows higher transconductance in linear region. The saturtion drive current is lower, compared to the conventional BF2-doped control. In addition, In-doped devices also shows improved DIBL, Ion-Ioff current ratio and transistor breakdown voltage. Finally, by increasing the indium implant energy, devices result in an improved transconductance, reduced DIBL and hot-carrier degradation, while suffering larger junction leakage and capacitance. Excellent PMOS short channel effect is achieved by using a high-energy, large tilt angle arsenic implant as a P-channel halo. For the first time, it was found that the dopant profile of halo was implanted through the poly-silicon gate. The channel concentration is modulated not only laterally from the gate edge but also vertically from the top of the polysilicon gate and this resulted in very flat short channel behavior. The effect of the arsenic halo implant was comprehensively studied and well characterized to explain this specific phenomenon. The gate-oxide integrity was examined by QBD(charge to break down). Excellent performance of 0.12 mm PMOSFET is also demonstrated in this work. Finally, an alternative approach for the extraction of effective channel length, Leff, using a modified capacitance-voltage (C-V) method [the capacitance-ratio (C-R) method], which considers depletion effect compensation is proposed. In general, we define Leff = Lmask - △L, where △L is the sum of the polysilicon gate lithography bias and two times the overlap length of the polysilicon gate and source/drain (S/D) extension (△L=Lpb+2Lovlap). Using the modified C-V method, more consistent and reasonable Leff data can be extracted as compared to those obtained using the newest current-voltage (I-V) method (shift and ratio method). In using the proposed C-R method, we can electrically measure the exact Lpb and Lovlap numbers that can both be used as process monitor parameters. The within-wafer uniformities of Leff (or △L), Lpb and Lovlap have also been checked among devices of various sizes. After the Leff is extracted, a stable S/D resistance Rsd, with Vg independence, is determined and verified using the I-V method. The parasitic capacitance Cgd is another extracted parameter that is as important as Rsd in SPICE modeling for Metal-Oxide-Semiconductor applications.