數位多模式基頻收發機之里德-所羅門碼編/解碼器設計

Abstract

由於航空交通量大幅增加，傳統飛航裝備與系統漸不符合民航界需求，特高頻的飛機通訊定址與回報系統 ( ACARS )雖然目前廣泛被使用，但其位元傳輸率偏低，通訊容量小已不敷航空通訊應用內容與數量之用。因此 國際民航組織(ICAO)等組織便制訂了一套新的航空通訊系統，特高頻數位鏈結 (VDL)，其數據傳輸率高且通訊容量大將取代 ACARS，成為下一代陸空通訊的主流。 本論文之目的在於設計適用於VDL第2模式基頻接收機的里德-所羅門碼編/解碼器，編/解碼器的設計必須考慮里德-所羅門碼的參數，因此選擇合適的演算法為首要工作，進一步的在設計編/解碼器電路時，實現對應於演算法的電路. 這些主要的模組包括 病徵值計算器、錯誤多項式產生器、錯誤位置多項式產生器、錯誤強度多項式產生器等等。本論文採用C語言和Matlab來進行編/解碼器的設計和驗證編/解碼器的正確性，並且針對編/解碼器中的各個演算法單元，利用VHDL進行硬體設計。本論文之結果可提供符合需求的編/解碼器架構，以協助建立國內下一代陸空通訊系統的關鍵技術，和培植自行研發陸空通訊無線接收機的能

The currently used air-ground communication system is the Aircraft Communication Addressing and Reporting System (ACARS). Due to its low data transmission rate and small communication capacity, ACARS cannot cope with the rapid growth of air traffic. Thus, ICAO embarked on definition of a new standard for aeronautical communication. This is the VHF digital link (VDL); it has higher transmission rate and large capacity. The VDL will gradually replace the ACARS and become the key VHF data link system for the next generation air-ground data communication. The object of this thesis is to design a Reed-Solomon (RS) codec for VDL mode2 baseband transceiver. The key modules for the codec include the syndrome calculator, error polynomial producer, error location producer, and the error magnitude producer. To reduce the chip area, we employ a time-sharing architecture and use a minimum number of multipliers in each module. We use C and Matlab to verify the codec function and evaluate its performance. Then, we use VHDL to model the codec behavior and implement it using a FPGA. The result of this thesis can help to built a complete VDL mode 2 transceiver, and to establish the key technology for the next generation air-ground communications.