標題: 多工單等級之平行機台排程問題研究-以IC封裝廠為例
The Study on Parallel Machine Scheduling Problem with Consideration of Multiple-priority Jobs and Its Application on IC Assembly Scheduling
作者: 賴春美
鍾淑馨
彭文理
工業工程與管理學系
關鍵字: 生產規劃;產品組合;交期指派;平行機台排程問題;整數規劃;production planning;product mix;due date assignment;parallel-machine scheduling;integer programming
公開日期: 2006
摘要: 在競爭市場中,晶圓製造在追求利潤時,必須充分考慮產能有效率的被利用。本文主要研究IC封裝排程問題,以最小化總工作負荷為衡量績效。IC封裝製程的生產特色為產品多樣少量且生產時間短。本文探討IC封裝實務因素之平行機台排程問題。此排程問題具有多工單等級、工作產品群組、工作產品別相關之處理時間、順序相關之設置時間及產能等限制,其求解比典型的平行機台排程問題更加困難。本文提出目標函數為最小化總工作負荷之IC封裝製程排程問題的整數規劃模式。本文利用數學規劃軟體CPLEX,結合有效的運算策略,則在可接受的時間內,可利用此模式求得實務問題的可行解。此外,本文也提出一啟發式演算法,並測試啟發式演算法之求解品質及其在實務上問題的應用。 由於晶圓製造之製程複雜、週期時間長、再迴流生產及批次機台等生產特性,使得生產週期時間估算困難。IC封裝須待晶圓之實貨到臨才能加工,封裝之到貨預估模式即為晶圓交期指派模式,因此本文先針對晶圓製造提出交期指派模式,利用此模式可在產品組合隨時間改變之環境下求得符合目標達交率之交期,以作為IC封裝排程之依據。
In order to increase a company’s competition edge and profitability, an Integrated-Circuit (IC) manufacturer needs to utilize its existed capacity efficiently. This dissertation studies the IC assembly scheduling problem (ICASP) with the objective of minimizing the total machine workload. The IC assembly scheduling problem (ICASP) is a practical generalization of the classical parallel-machine scheduling problem. Since the ICASP involves constraints on precedence, job clusters, job-cluster dependent processing time, machine capacity, and sequence dependent setup times, it is more difficult to solve than the classical parallel machine scheduling problem. In this dissertation, we formulate the ICASP as an integer programming problem with minimizing the total machine workload to simultaneously assign jobs to machines and sequence the jobs on each machine. By using the powerful CPLEX with effective implementation strategies, the feasible solutions of the real-world ICASP problem can be obtained within reasonable amount of time. An effective and efficient algorithm is also proposed for solving large scale problems. Wafer fabrication determines to a large extend the production plan of the whole semiconductor manufacturing due to its high complexity and long manufacturing process time. The accuracy of due-date assignment for wafer fabrication strongly influences the efficiency of the scheduling of downstream (back-end) operations. In this dissertation, we also proposed a due-date assignment model for wafer fabrication where the product mix periodically changes.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT008833809
http://hdl.handle.net/11536/69112
顯示於類別:畢業論文


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