永磁同步馬達位置控制之FPGA晶片研製

Abstract

本論文以場效型可規劃邏輯陣列(FPGA)晶片為基礎，整合數位邏輯晶片與Nios處理器於單一顆FPGA晶片中，以實現永磁同步馬達之位置控制。在數位邏輯晶片中，以硬體描述語言實現向量控制法則的電流及編碼器回授檢測、座標轉換、正弦波脈寬調變、電流迴路之PI控制器等功能模組；而在Nios處理器中，以C語言實現轉速PI控制器、位置P控制器、以及資料傳輸用的SECS通訊協定。在數值系統設計上使用Q格式觀念實現正規化，以提高數值運算的精確度。

在實驗系統的建置方面，採用Nios發展套件為永磁同步馬達的控制核心，並配合一套包含驅動處理、回授處理、介面擴充功能的外部電路，來完成永磁同步馬達位置控制系統的建構，並經由實驗數據的量測分析與控制參數的調整，而獲取系統較佳的控制效能表現。同時，在電腦端設計了一套人機介面，並透過RS232連接線以SECS通訊協定來作資料傳輸，以實現遠端監控的功能。

In this thesis, a FPGA (Field Programmable Gate Array)-based Chip design is taken to implement a position control chip conceptual core for permanent magnet synchronous motor (PMSM) drive, and the control chip integrate digital logic IC and Nios processer in single FPGA chip. The function of the digital logic IC includes current and encoder feedback processing, coordination transformation, sinusoidal pulse width modulation (SPWM), current-loop proportional-integration (PI) controller, and so on. And the function of Nios processer includes speed-loop proportional-integration (PI) controller, position-loop proportional controller, and SECS communicating protocol. All the numerical system are normalized with Q-format concept to increase the precision during the operation.

As for the experimental setup and related system collocation, it is construct from the Nios developement kit of the core concept for controlling a PMSM, and peripheral circuit boards for motor drive, signal feedback, and interface expand function. Besides, it demonstrates the effectiveness of the proposed FPGA-based control system for the performance improvement for PMSM drive can be achieved by adjustment of the control parameter and measurement and analysis of experimental data. It also develop a user interface in PC-base by SECS protocol through RS232 connecter to communicate with FPGA chip, and fulfill the function of remote control and monitor.