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dc.contributor.authorKuo, Yu-Tingen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorLi, Yueh-Taien_US
dc.contributor.authorLin, Chou-Kunen_US
dc.contributor.authorLiu, Chih-Weien_US
dc.date.accessioned2014-12-08T15:01:58Z-
dc.date.available2014-12-08T15:01:58Z-
dc.date.issued2008en_US
dc.identifier.isbn978-83-88309-47-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/697-
dc.description.abstractThis paper presents a low-power filter bank design for digital hearing aids, which is compliant with the ANSI S1.11 standard. A multi-rate filtering algorithm and its coefficient design method are proposed, which reduce 94% multiplications. The power dissipation is further reduced by 31% and 35% with switch activity reduction and multi-VDD silicon implementation respectively. The design has been implemented using the TSMC 0.13 mu m CMOS technology and consumes only 79 mu W for 24KHz 18-band audio processing.en_US
dc.language.isoen_USen_US
dc.subjectHearing aiden_US
dc.subjectfilter banken_US
dc.subjectlow poweren_US
dc.titleLow-Power ANSI S1.11 Filter Bank for Digital Hearing Aidsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalICSES 2008 INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS, CONFERENCE PROCEEDINGSen_US
dc.citation.spage347en_US
dc.citation.epage350en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000265166600081-
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