鐵電記憶體場效式電晶體應用之鐵電薄膜材料製程及特性研究

Abstract

單一電晶體鐵電記憶體因其較小的元件面積和非破壞性讀寫的操作方式等優點而成為下一世代的鐵電記憶體。在本研究中，鋯鈦酸鉛和鑭取代鈦酸鉍這兩組鐵電薄膜同樣地被證實是可以整合在具有金屬-鐵電薄膜-絕緣層-半導體 (MFIS) 這樣疊層閘極結構的單一電晶體記憶體中，另外在這種MFIS的閘極電容中，氧化鋁因其比具有相同等效氧化層厚度的氧化矽較高的介電常數和較低的漏電流而被視為適當的絕緣層材料來使用。首先，比起傳統的MFM電容而言，MFIS閘極電容被證明不但具有類似的記憶效應而且其漏電流也比MFM電容來得低；在鋯鈦酸鉛/氧化鋁/矽基板的MFIS電容中，因為發現在氧化鋁基板上成長富鈦成分的鋯鈦酸鉛比起富鋯成分的鋯鈦酸鉛具有較低的的鈣鈦礦轉換溫度，所以鈦酸鉛緩衝層被用來抑止在鋯鈦酸鉛/氧化鋁/矽基板的MFIS電容中Pyrochlore相的生成，另外，和富鋯鋯鈦酸鉛/鈦酸鉛/氧化鋁/矽基板電容因電荷注入所得到的記憶效應來做比較，富鈦鋯鈦酸鉛/鈦酸鉛/氧化鋁/矽基板電容所得到的是鐵電式的記憶效應；在鑭取代鈦酸鉍/氧化鋁/矽基板電容中，和退火溫度相關的效應被研究後因而發現由較高溫度退火得到的鑭取代鈦酸鉍/氧化鋁/矽基板電容會有較大記憶窗和較低的漏電流，經由進一步地探討其界面反應後可以發現，氧化鋁絕緣層與鐵電薄膜和矽基板在退火時的反應應該是電容低漏電的主因，另外，較高溫度退火後所得到有較大晶粒的鑭取代鈦酸鉍鐵電薄膜亦是造成較大的記憶窗的原因之一；最後，單一電晶體記憶體元件的相關關鍵製程根據在之前在MFIS電容特性上的研究結果而被發展，經過實際上單一電晶體記憶體元件的記憶特性量測後可以發現，本研究所發展的鐵電薄膜製程不但可以在MFIS電容上具有優異的記憶特性，此外配合相關的半導體製程，本研究所發展的MFIS疊層閘極結構更是被證實可以進一步地應用在真實的記憶元件上。

Among many kinds of ferroelectric random access memories (FeRAMs), one-transistor (1T) ferroelectric MOSFET (FeMOSFET) type memory is very attractive due to the same small 1T cell and nondestructive read-out (NDRO) operation. Pb(ZrxTi1-x)O3 (PZT) and Bi3.25La0.75Ti3O12 (BLT) ferroelectric thin films have been integrated in 1T memory with metal-ferroelectric-insulator-semiconductor (MFIS) gate structure. Al2O3 was found to be a suitable insulator material in these MFIS capacitors due to the higher dielectric constant and lower leakage current than those of SiO2 with the same equivalent oxide thickness (EOT). Besides, the MFIS capacitors were demonstrated to have similar memory effect and lower leakage current in comparison with the metal-ferroelectric-metal (MFM) capacitors. In PZT/Al2O3/Si capacitors, the usage of PbTiO3 (PTO) seeding layer was found to be able to inhibit the formation of pyrochlore phase because Ti-rich PZT films have lower perovskite transformation temperatures than those of Zr-rich PZT films on Al2O3 buffered Si. Besides, the memory effect of Ti-rich PZT/PTO/Al2O3/Si capacitors was attributed to the ferroelectricity in contrast to those of Zr-rich PZT capacitors derived from charge injection. For BLT/Al2O3/Si capacitors, the effects of annealing temperature were investigated and the capacitors annealed in higher temperatures would have larger memory window and lower leakage current. Furthermore, the interface reaction was studied so that the lower leakage current of capacitors was suggested to be the result of the high temperature reaction of insulator with ferroelectric and Si though the larger grain size of BLT films annealed in the higher temperatures would correspond to the larger memory window of capacitors. The related processing for 1T memory devices were developed in this thesis and the device characteristics were also demonstrated.