標題: 數位無線通訊系統應用之低電壓高功率砷化鎵場效電晶體研究
Low-Voltage High-Power GaAs FET’s for Digital Wireless Communication System Applications
作者: 陳仕鴻
CHEN SZU HUNG
張翼
張立
Edward Yi Chang
Li Chang
材料科學與工程學系
關鍵字: 金半場效電晶體;耗竭型假晶式高電子遷移率電晶體;加強型假晶式高電子遷移率電晶體;相位移光罩;MESFET;D-PHEMT;E-PHEMT;PSM
公開日期: 2002
摘要: 本論文針對應用於低電壓操作無線通訊之砷化鎵場效電晶體作一系列之探討。 所研究的砷化鎵場效電晶體包括: 金屬半導體場效電晶體 (MESFET),耗竭型假晶式高電子遷移率電晶體 (D-PHEMT) 與加強型假晶式高電子遷移率電晶體 (E-PHEMT)。 所完成的MESFET元件,夾止電壓為-2.8V,飽和汲極電流為250mA/mm,最大互導為129mS/mm,汲極-閘極崩潰電壓為16V (定義於閘極電流達到1mA/mm時的汲極對閘極電壓)。同時並針對20mm大小的元件,對整片晶片上的元件作夾止電壓量測統計,標準偏差均能維持在150 mV 以下 (或是5%之內)。在功率特性方面,於1.9GHz於class AB條件下 (3.6 V偏壓與80 mA汲極電流),最大輸出功率為32.98 dBm,且於輸出功率為32.52 dBm時,功率增加效益為53.3%。由此數據顯示,所研發之MESFET可應用於 DCS手機系統。若輸入訊號為1.9 GHz IS-95 CDMA signal,並在相同的偏壓條件下作測試,可發現在28 dBm輸出功率時,元件在距離中心頻率分別為1.25 MHz與2.25 MHz的 adjacent channel power rejection (ACPR) 分別為 -29.5 dBc與 -44.9dBc,符合IS-95 CDMA系統規格要求。 所完成的D-PHEMT元件,其尺寸大小為6.72 mm,夾止電壓為 –1.1V,飽和汲極電流密度為265 mA/mm,最大互導為354 mS/mm (在Vds=2 V時)。在Vds=1.2 V時,其最大互導仍有325 mS/mm的表現。另外,崩潰電壓測得為11 V (定義於閘極電流達到100μA/mm時的汲極對閘極電壓)。在的功率特性方面,6.72 mm的PHEMT元件在1.9 GHz,於class AB條件下(1.2 V 偏壓與100 mA汲極電流),當輸出功率為22.18 dBm時,功率增加效率為43.62%,其線性增益為11.78dB。。若此元件在1.9 GHz之π/4QPSK(Quadrature Phase SHIFT Keying)調變PHS訊號下及相同的偏壓條件下,當輸出功率為22 dBm時,功率增加效益可達41.31%,增益為6.3 dB。此時元件在距離中心頻率分別為600 kHz的 adjacent channel leakage power (Padj)為-56.86 dBc。因此所研發完成的PHEMT元件,在極低的1.2V汲極偏壓與100mA汲極電流操作下,仍具有極高的功率增加效益,且由於良好的線性度,所以有低失真(low distortion)的表現。 所完成的E-PHEMT元件,其尺寸大小為20mm,夾止電壓為 0.09V,最大飽和汲極電流 (Imax)為350 mA/mm,最大互導為490 mS/mm。因此除了高互導外,此元件亦具有極高的Imax值。此極高的Imax值,為使用Al0.3Ga0.7As作為間隔層的緣故。在的功率特性方面,20mm的PHEMT元件在1.9 GHz,於class AB條件下(3.0V偏壓與700 mA汲極電流),飽和輸出功率高達34.1dBm (2.57W, 128mW/mm),功率增加效益為64.5%。當汲極偏壓為2.4V,汲極電流為500mA時,飽和輸出功率亦達32.25dBm,功率增加效率為61.45%。若阻抗匹配至最大功率增加效率,可得最大功率增加效益為78.5%,此時輸出功率仍可維持30.82dBm,增益為14.18dB。 因此,本論文研究已發展完成適合低電壓操作的無線通訊用砷化鎵功率放大器。砷化鎵MESFET與 PHEMT均展現良好的功率效益與線性度。所研發的砷化鎵功率放大器具有極佳的潛力應用於未來先進之低電壓無線通訊系統中。
In this dissertation, high power GaAs-based FETs were developed for low voltage wireless communication applications. The developed GaAs-based FETs include MESFETs (Metal Semiconductor Field Effect Transistors), D-PHEMTs (depletion-mode pseudomorphic high electron mobility transistors), and enhancement-mode PHEMTs (E-PHEMTs). The process of the ion-implanted planar gate MESFET contains double Be implantation to trim the drain saturation current of the device to the desired level and reduce the surface and substrate defect trapping effects. The MESFETs shows good device uniformity and excellent power performance. The average pinch-off voltage of the 20 mm devices is -2.81 V with a standard deviation of 120 mV across a 3-inch wafer. The 1 µm × 20 mm MESFET exhibits a high output power of 33.85 dBm (121.3 mW/mm) with associated power-added efficiency (PAE) of 54.6 % at Vds =3.4 V with quiescent Ids of 1000 mA at 1.9 GHz. Under IS-95 CDMA modulation signal at 1.9 GHz and biased at Vds =3.6 V with quiescent Ids of 80 mA, the device has adjacent channel leakage power (Padj) of –29.5 dBc at 1.25 MHz offset and –44.9 dBc at 2.25 MHz offset from the center frequency at output power level of 28 dBm. The test data show that the developed double Be-implanted power MESFETs deliver high power, high efficiency and demonstrate good linearity under digital modulation signal. The superior performance of the MESFETs shows the developed devices are suitable for low-voltage digital wireless communication system applications, such as DCS (Digital Cellular System) and CDMA (Code Division Multiple Access). High power dual planar-doped AlGaAs/InGaAs D-PHEMTs and E-PHEMTs are also developed. When testing condition is at 1.9 GHz and Vds= 1.2 V under class AB condition, the 6.72-mm D-PHEMT has a maximum PAE of 43.62 % with an associated output power of 22.18 dBm. The performance of the D-PHEMTs under digital modulation signal is also evaluated. At Vds= 1.2 V under 1.9 GHz π/4-shifted QPSK PHS signal, the device shows an output power of 22 dBm with a Padj of -56.86 dBc at 600 kHz apart from 1.9 GHz center frequency and the linear PAE is 41.31 %. The 6.72-mm PHEMT meets the PHS specifications and the measured results are the first report on the power PHEMT for 1.2-V PHS application. When 20.16-mm PHEMT was qualified under 1.9 GHz IS-95 CDMA modulation signal, the results show the device meets the CDMA specifications at both Vds= 3.0 V and Vds= 2.4 V. When the linear output power is 28 dBm, the device has a PAE of 37.8 % at Vds= 3.0 V and PAE of 30.2 % at Vds= 2.4 V. At Vds= 2.4 V, the device has Padj of -31.46 dBc at 1.25 MHz and –48.83 dBc at 2.25 MHz offset from the center frequency when output power is 28 dBm. This is also the first report on the power PHEMT for 2.4-V CDMA application. In addition, high power E-PHEMTs were also fabricated. The device has VT of 90 mV, maximum gm of 490 mS/mm, and drain current density of 350mA/mm (at Vgs = 1.0 V). When tested at 1.9 GHz, the 3.36-mm E-PHEMT exhibits a high power density of 247 mW/mm at 3.6 V, 196 mW/mm at 3 V, 152 mW/mm at 2.4 V and 63 mW/mm at 1.2 V. The 20.16-mm E-PHEMT shows 34.1 dBm (128 mW/mm) output power with PAE of 64.5 % at Vds = 3.0V. At Vds = 2.4 V, a maximum saturated output power of 32.25 dBm and maximum PAE of 78.5 % is achieved. At 1.2 V, the E-PHEMT also delivered a high output power of 29.75 dBm (47 mW/mm) with maximum PAE of 51.6 %. The 3.36-mm E-PHEMT was also qualified by 1.9 GHz π/4-shifted QPSK modulated PHS signal. The test condition is at Vds = 2.4 V and quiescent Ids = 30 mA. The device shows a linear PAE of 35.1 % with associated power gain of 15.5 dB at output power of 22.4 dBm. The Padj of the device is –56.6 dBc at 600 kHz apart from the center frequency. The 3.36-mm E-PHEMT meets PHS specifications at Vds = 2.4 V. The results demonstrate both MESFETs and PHEMTs developed show high power, high efficiency and high linearity at low voltage operation. The developed GaAs FETs have great potential for advanced low voltage wireless communication system applications. Finally, a novel T-shaped gate process with PSM and silicon nitride etch-back technologies is also described in this dissertation. The phase shift mask and i-line stepper with a small σ were used to improve the resolution and DOF of the lithography process. The T-shaped gate with a length of 0.167 μm was achieved. This novel process is a high-throughput process of fabrication of T-shaped gate by using i-line exposure with PSM compared to the conventional E-beam lithography technology and can be used for mass production of integrated circuits.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT910159004
http://hdl.handle.net/11536/69898
顯示於類別:畢業論文