标题: 数位无线通讯系统应用之低电压高功率砷化镓场效电晶体研究
Low-Voltage High-Power GaAs FET’s for Digital Wireless Communication System Applications
作者: 陈仕鸿
CHEN SZU HUNG
张翼
张立
Edward Yi Chang
Li Chang
材料科学与工程学系
关键字: 金半场效电晶体;耗竭型假晶式高电子迁移率电晶体;加强型假晶式高电子迁移率电晶体;相位移光罩;MESFET;D-PHEMT;E-PHEMT;PSM
公开日期: 2002
摘要: 本论文针对应用于低电压操作无线通讯之砷化镓场效电晶体作一系列之探讨。
所研究的砷化镓场效电晶体包括: 金属半导体场效电晶体 (MESFET),耗竭型假晶式高电子迁移率电晶体 (D-PHEMT) 与加强型假晶式高电子迁移率电晶体 (E-PHEMT)。
所完成的MESFET元件,夹止电压为-2.8V,饱和汲极电流为250mA/mm,最大互导为129mS/mm,汲极-闸极崩溃电压为16V (定义于闸极电流达到1mA/mm时的汲极对闸极电压)。同时并针对20mm大小的元件,对整片晶片上的元件作夹止电压量测统计,标准偏差均能维持在150 mV 以下 (或是5%之内)。在功率特性方面,于1.9GHz于class AB条件下 (3.6 V偏压与80 mA汲极电流),最大输出功率为32.98 dBm,且于输出功率为32.52 dBm时,功率增加效益为53.3%。由此数据显示,所研发之MESFET可应用于 DCS手机系统。若输入讯号为1.9 GHz IS-95 CDMA signal,并在相同的偏压条件下作测试,可发现在28 dBm输出功率时,元件在距离中心频率分别为1.25 MHz与2.25 MHz的 adjacent channel power rejection (ACPR) 分别为 -29.5 dBc与 -44.9dBc,符合IS-95 CDMA系统规格要求。
所完成的D-PHEMT元件,其尺寸大小为6.72 mm,夹止电压为 –1.1V,饱和汲极电流密度为265 mA/mm,最大互导为354 mS/mm (在Vds=2 V时)。在Vds=1.2 V时,其最大互导仍有325 mS/mm的表现。另外,崩溃电压测得为11 V (定义于闸极电流达到100μA/mm时的汲极对闸极电压)。在的功率特性方面,6.72 mm的PHEMT元件在1.9 GHz,于class AB条件下(1.2 V 偏压与100 mA汲极电流),当输出功率为22.18 dBm时,功率增加效率为43.62%,其线性增益为11.78dB。。若此元件在1.9 GHz之π/4QPSK(Quadrature Phase SHIFT Keying)调变PHS讯号下及相同的偏压条件下,当输出功率为22 dBm时,功率增加效益可达41.31%,增益为6.3 dB。此时元件在距离中心频率分别为600 kHz的 adjacent channel leakage power (Padj)为-56.86 dBc。因此所研发完成的PHEMT元件,在极低的1.2V汲极偏压与100mA汲极电流操作下,仍具有极高的功率增加效益,且由于良好的线性度,所以有低失真(low distortion)的表现。
所完成的E-PHEMT元件,其尺寸大小为20mm,夹止电压为 0.09V,最大饱和汲极电流 (Imax)为350 mA/mm,最大互导为490 mS/mm。因此除了高互导外,此元件亦具有极高的Imax值。此极高的Imax值,为使用Al0.3Ga0.7As作为间隔层的缘故。在的功率特性方面,20mm的PHEMT元件在1.9 GHz,于class AB条件下(3.0V偏压与700 mA汲极电流),饱和输出功率高达34.1dBm (2.57W, 128mW/mm),功率增加效益为64.5%。当汲极偏压为2.4V,汲极电流为500mA时,饱和输出功率亦达32.25dBm,功率增加效率为61.45%。若阻抗匹配至最大功率增加效率,可得最大功率增加效益为78.5%,此时输出功率仍可维持30.82dBm,增益为14.18dB。
因此,本论文研究已发展完成适合低电压操作的无线通讯用砷化镓功率放大器。砷化镓MESFET与 PHEMT均展现良好的功率效益与线性度。所研发的砷化镓功率放大器具有极佳的潜力应用于未来先进之低电压无线通讯系统中。
In this dissertation, high power GaAs-based FETs were developed for low voltage wireless communication applications. The developed GaAs-based FETs include MESFETs (Metal Semiconductor Field Effect Transistors), D-PHEMTs (depletion-mode pseudomorphic high electron mobility transistors), and enhancement-mode PHEMTs (E-PHEMTs).
The process of the ion-implanted planar gate MESFET contains double Be implantation to trim the drain saturation current of the device to the desired level and reduce the surface and substrate defect trapping effects. The MESFETs shows good device uniformity and excellent power performance. The average pinch-off voltage of the 20 mm devices is -2.81 V with a standard deviation of 120 mV across a 3-inch wafer. The 1 µm × 20 mm MESFET exhibits a high output power of 33.85 dBm (121.3 mW/mm) with associated power-added efficiency (PAE) of 54.6 % at Vds =3.4 V with quiescent Ids of 1000 mA at 1.9 GHz. Under IS-95 CDMA modulation signal at 1.9 GHz and biased at Vds =3.6 V with quiescent Ids of 80 mA, the device has adjacent channel leakage power (Padj) of –29.5 dBc at 1.25 MHz offset and –44.9 dBc at 2.25 MHz offset from the center frequency at output power level of 28 dBm. The test data show that the developed double Be-implanted power MESFETs deliver high power, high efficiency and demonstrate good linearity under digital modulation signal. The superior performance of the MESFETs shows the developed devices are suitable for low-voltage digital wireless communication system applications, such as DCS (Digital Cellular System) and CDMA (Code Division Multiple Access).
High power dual planar-doped AlGaAs/InGaAs D-PHEMTs and E-PHEMTs are also developed. When testing condition is at 1.9 GHz and Vds= 1.2 V under class AB condition, the 6.72-mm D-PHEMT has a maximum PAE of 43.62 % with an associated output power of 22.18 dBm. The performance of the D-PHEMTs under digital modulation signal is also evaluated. At Vds= 1.2 V under 1.9 GHz π/4-shifted QPSK PHS signal, the device shows an output power of 22 dBm with a Padj of -56.86 dBc at 600 kHz apart from 1.9 GHz center frequency and the linear PAE is 41.31 %. The 6.72-mm PHEMT meets the PHS specifications and the measured results are the first report on the power PHEMT for 1.2-V PHS application. When 20.16-mm PHEMT was qualified under 1.9 GHz IS-95 CDMA modulation signal, the results show the device meets the CDMA specifications at both Vds= 3.0 V and Vds= 2.4 V. When the linear output power is 28 dBm, the device has a PAE of 37.8 % at Vds= 3.0 V and PAE of 30.2 % at Vds= 2.4 V. At Vds= 2.4 V, the device has Padj of -31.46 dBc at 1.25 MHz and –48.83 dBc at 2.25 MHz offset from the center frequency when output power is 28 dBm. This is also the first report on the power PHEMT for 2.4-V CDMA application.
In addition, high power E-PHEMTs were also fabricated. The device has VT of 90 mV, maximum gm of 490 mS/mm, and drain current density of 350mA/mm (at Vgs = 1.0 V). When tested at 1.9 GHz, the 3.36-mm E-PHEMT exhibits a high power density of 247 mW/mm at 3.6 V, 196 mW/mm at 3 V, 152 mW/mm at 2.4 V and 63 mW/mm at 1.2 V. The 20.16-mm E-PHEMT shows 34.1 dBm (128 mW/mm) output power with PAE of 64.5 % at Vds = 3.0V. At Vds = 2.4 V, a maximum saturated output power of 32.25 dBm and maximum PAE of 78.5 % is achieved. At 1.2 V, the E-PHEMT also delivered a high output power of 29.75 dBm (47 mW/mm) with maximum PAE of 51.6 %. The 3.36-mm E-PHEMT was also qualified by 1.9 GHz π/4-shifted QPSK modulated PHS signal. The test condition is at Vds = 2.4 V and quiescent Ids = 30 mA. The device shows a linear PAE of 35.1 % with associated power gain of 15.5 dB at output power of 22.4 dBm. The Padj of the device is –56.6 dBc at 600 kHz apart from the center frequency. The 3.36-mm E-PHEMT meets PHS specifications at Vds = 2.4 V.
The results demonstrate both MESFETs and PHEMTs developed show high power, high efficiency and high linearity at low voltage operation. The developed GaAs FETs have great potential for advanced low voltage wireless communication system applications.
Finally, a novel T-shaped gate process with PSM and silicon nitride etch-back technologies is also described in this dissertation. The phase shift mask and i-line stepper with a small σ were used to improve the resolution and DOF of the lithography process. The T-shaped gate with a length of 0.167 μm was achieved. This novel process is a high-throughput process of fabrication of T-shaped gate by using i-line exposure with PSM compared to the conventional E-beam lithography technology and can be used for mass production of integrated circuits.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT910159004
http://hdl.handle.net/11536/69898
显示于类别:Thesis