無線都會網路內接收機的硬體設計與實現

Abstract

隨著近年來Wi-Fi(802.11x)產品的日漸普及與3G無線通訊技術的推波助瀾下，無線通訊技術一直都是大家所注目的焦點，其中，無線都會網路(Wireless Metro Area Connectivity)更是以IEEE 802.16為標準。本論文的目的即是以IEEE 802.16a的實體層為基本，設計一個內接收機的系統；從封包的偵測、頻率偏移的估計與補償、邊界的同步乃至於通道特性的評估，設計出一個整合的系統。硬體上，我們善用記憶體配置的方法，找出訊號的自相關性以偵測封包以及估計頻率偏移；以數位座標旋轉演算法(Coordinate Rotation Digital Computer，CORDIC)為基礎設計出一個改良的硬體以補償頻率偏移；接著利用匹配濾波器來同步調整符元(Training Symbol)間的邊界，亦同時估計出循環字首(Cyclic Prefix，CP)的長度；最後用Maximum Likelihood演算法求得通道特性用以作補償之用。

IEEE 802.16a is the standard for the wireless metro area connectivity (Wireless MAN). In this thesis, our goal is to develop cost-effective circuitry architecture for the inner receiver system based on the IEEE 802.16a standard. We design an integrated hardware system which contains packet detection, frequency offset estimation, frame synchronization and channel estimation. The hardware architecture is composed of four computation units and a shared memory bank, connected with a data bus. The four computation units are an auto-correlation engine for joined packet-detection /frequency-offset-estimation, a CORDIC (coordinate rotation digital computer) engine for frequency error compensation, a match filter engine for preamble detection, and the circuitry performing maximum likelihood channel estimation. The proposed integrated circuit architecture is area-efficient because of the high reusability of memory modules, which are commonly known to occupy most of the silicon area. Finally, the design is ported to an Altera FPGA development board. The target system clock rate is running at 56 MHz, which is twice of the sample rate of IEEE 802.16a transmission signal for MMDS.