動態臨界電壓金氧半電晶體在不同溫度與結構之可靠性分析

Abstract

本篇論文是在研究動態臨界電壓金氧半電晶體P通道元件之可靠性。面對將來低耗能、高速度的元件要求，動態臨界電壓金氧半電晶體因為有較低的臨界電壓、以及良好的元件操作特性，而被視為一個很有發展潛力的元件。至今已有許多研究顯示，動態臨界電壓金氧半電晶體N通道元件在元件特性、以及可靠度上，都表現的比一般的元件要好；但有關P通道元件的資料卻依然缺乏。因此我們製作了不同閘極結構之動態臨界電壓金氧半電晶體P通道元件，對其進行有系統的可靠性研究，以期能夠實現動態臨界電壓金氧半電晶體在電路上的整體應用。 在本篇論文中，首先發現不同閘極結構在一般操作模式下的可靠度特性差異。對有基板電極的元件 (如H-閘及T-閘)，由於基極電流可有效疏導基板的電荷，使其不再累積，故可有效降低撞擊游離發生的機率，使元件特性在長時間工作後的表現，相對於沒有基板電極的元件，都有明顯的改善。 而在動態臨界電壓的操作模式之下，由於閘極與基極的連接有效降低垂直電場強度，撞擊游離產生的載子不易跨越矽/二氧化矽的界面能障，從而降低長時間工作後臨界電壓的飄移量。但在轉導特性方面，由於動態臨界電壓的操作模式，對於界面電荷的改變較為敏感，因而放大了這些電荷所造成的轉導劣化，使動態臨界電壓金氧半電晶體的表現反較一般電晶體為差。而在驅動電流的表現上，由於轉導的大幅度劣化，動態臨界電壓金氧半電晶體的表現也較差。 在溫度效應上，動態臨界電壓金氧半電晶體較一般電晶體對溫度更敏感；隨著溫度的上升及下降，在臨界電壓以及轉導上都有更大比率的下降及上升。在可靠度方面，由於溫度上升時，會抑制撞擊游離的發生，所以隨著溫度的上升，元件的劣化幅度也隨之縮小。從0度到100度的可靠性測試，都顯示相同的趨勢。在基板濃度的效應上，不同摻雜濃度對於動態臨界電壓操作模式、以及撞擊游離的影響均很大。在元件特性上，高摻雜濃度會使動態臨界電壓模式較一般模式展現出更好的改善。但高基板摻雜濃度也提高撞擊游離發生率，所以長時間工作後，兩種操作模式之下劣化情形，都更形嚴重。

In this study, the reliability of p-channel dynamic threshold voltage MOSFETs (DTMOS) is characterized. With increasing demands in high-speed and low-power digital electronics in recent years, DTMOS with its lower threshold voltage, higher transconductance, and enhanced current drive capability is very promising for future ULSI CMOS applications. However, the hot-carrier reliability data of p-channel DTMOS are still lacking, and this motivates us to carry out this work. First, the characteristics of various gate structures including T-gate and H-gate were investigated. Since the presence of substrate contacts enables the efficient removal of charge in the body region, thus prevents carrier accumulations in the body region, and therefore reduces the impact ionization rate, devices with T-gate and H-gate exhibit better performance compared to the standard devices without substrate contacts. Under DT-mode, by tying the gate to the body, the vertical electric field across the oxide is greatly reduced. So the probability of generated holes to surmount the Si/SiO2 energy barrier is greatly reduced. As a result, the threshold voltage shift is reduced. Since the effectiveness of the gate bias is amplified under DT-mode, a small change in charge trapping and/or interface trap generation would result in a large transconductance change during stress, compared to the normal mode operation. This results in worsen stress-induced transconductance degradation. The on-state current of DT-mode device exhibits enhanced degradation than the normal mode device due to the enhanced transconductance degradation. Devices under DT-mode depict a larger temperature dependence on threshold voltage shift and transconductance degradation, decreasing and increasing more rapidly with the increasing and decreasing of temperature. It is also seen that devices stressed at higher temperature show less degradation. This is because impact ionization rate is decreased with increasing temperature. The effects of substrate doping concentration are also studied. It is found that for DT-mode, a higher substrate doping results in higher percentage change in device parameter. However, higher substrate doping concentration also increases the impact ionization rate, and aggravates stress-induced degradations under both normal and DT modes.