針對系統晶片匯流排功能驗證之研究

Abstract

藉由晶片匯流排的協定，使得系統單晶片設計中的矽智產單元群們能夠彼此溝通。由於這些矽智產單元經常是從不同的地方所取得，因此，確保全部的矽智產單元可以在整合成單晶片系統之後尚能正確地工作也就更顯重要。在這篇論文中，我們提出了一個以監視器為基礎的方法來實現晶片匯流排的認證測試。這個方法使用一個匯流排監視器來觀察匯流排系統中的互動行為，並且檢查其是否符合該晶片匯流排的協定。此外，為了描述晶片匯流排協定的規格，我們也提出了一個有限狀態機的模型。藉此，我們可以更有系統地從規格中粹取出所需之特性來。而且，由於該有限狀態機能正確地指出資料傳遞的時間點，我們便可以在執行模擬的同時，檢查資料傳遞的正確性。最後，針對系統晶片匯流排功能驗證，我們提出了一個合適的涵蓋率量度，來評估模擬的完整性。我們以兩種常見的晶片匯流排協定(WISHBONE和AMBA AHB)做為研究課題，來證明此方法的可行性。藉由一些實際電路的實驗，證實的確可以有效地驗證晶片匯流排的協定及偵測出電路的錯誤所在。

System-on-chip (SOC) designs use the on-chip bus (OCB) protocols to enable the communication among a set of IP cores. These IP components are usually obtained from different suppliers. Therefore, to guarantee that the IP components can work correctly after being integrated into a SOC design becomes more important. In this thesis, we propose a monitor-based approach for OCB compliance test. This approach employs a bus monitor to observe the interactive behavior among the bus system and check if it conforms to the OCB protocol. Moreover, we also propose a FSM model to describe the OCB protocol specification. Based on this model, we can extract the properties from the specification more systematically. Besides, due to that the FSM can exactly indicate when a data move occurs, we can check the data part of a bus transfer during the simulation. Finally, we propose an appropriate coverage metric to perform a quantitative analysis of simulation completeness on our OCB compliance test. To demonstrate our methodology, we illustrate two OCB protocols, WISHBONE and AMBA AHB, as the study cases. Experiments are conducted over some real designs and the experimental results show that we can verify the OCB protocols efficiently and detect the design errors when tests fail.