複晶矽薄膜電晶體之特性、機制與新結構之研究

Abstract

本論文主要探討複晶矽薄膜電晶體之各種尺寸效應，藉由製作具有各種不同條件的元件，元件的通道長度、寬度、厚度以及晶粒大小對尺寸效應的影響可以被詳細的分析探討，另外，我們也建立了相關物理模型來解釋所觀察到的撞擊游離效應，與實驗結果相比較，所建立的模型可以得到很好的一致性，藉由量測基板電壓，也探討了浮動基板所造成的基板效應。為了抑制複晶矽薄膜電晶體中嚴重的短通道效應，我們也在本論文中設計並製作了兩種新結構的複晶矽薄膜電晶體，藉由量測元件特性以及可靠度，我們發現所提出的新結構確實可以有效抑制短通道效應。 首先，我們著重在短通道效應的探討，除了習知的截止電壓偏移和高電場撞擊游離之外，我們發現基板電壓的變化和臨界電壓下滑現象(threshold voltage roll-off)有關，我們也觀察到由浮動基板中寄生雙極性電晶體(BJT)造成的閂鎖(latch up)現象，它會使元件呈現近似於數位態位轉變的特性，在次臨界區域有極為陡峭的電流爬升現象，同時，當關閉雙極性電晶體閂鎖現象時，發現由於基板累積的電洞需要被複合排除，所以出現磁滯效應(hysteresis)，隨著元件通道寬度變小或缺陷的增加，磁滯效應就可以被抑制。另外，在量測基板電流時，除了基板接觸和通道區之間的寄生穿隧電流之外，可以觀察到明顯的離子轟擊電流。我們建立了合理的物理機制來解釋所觀察到的撞擊游離現象，發現垂直電場的散射現象會影響到撞擊游離效應。 接下來我們研究複晶矽薄膜電晶體的窄通道效應，為了釐清旁側通道、通道邊緣缺陷和通道缺陷密度對窄通道效應的貢獻，我們設計了三組測試元件。利用多通道元件和單通道元件的特性比較，可以分別探討前述三項對窄通道效應的影響。最後得到的結論是：當通道寬度不夠窄的時候，活性離子蝕刻(RIE)在通道邊緣產生的缺陷會使元件特性劣化，但是當通道寬度非常小的時候，因為通道缺陷密度相對減少，就可以彌補活性離子蝕刻造成的特性劣化，而使得窄通道元件的特性變好。 為了抑制浮動基板效應，我們製作了具有超薄通道的複晶矽薄膜電晶體，同時，為了防止超薄通道造成極大的汲極源極寄生電阻會使元件特性劣化，我們應用了選擇性沉積的鎢薄膜覆蓋在汲極源極和閘極區域以減少寄生電阻，選擇性沉積鎢可以在低溫下自動選擇性沉積鎢金屬薄膜到矽或複晶矽材料上，而不會在氧化矽或氮化矽材質上沉積；具有鎢覆蓋汲極源極的元件和沒有鎢覆蓋汲極源極的元件相比，的確有較佳的驅動能力。同時，元件的寄生電阻也從元件特性中萃取出來，直接驗證了所設計結構確實降低了寄生電阻。由於通道縮小的時候，通道電阻變小，相對的寄生電阻對元件的特性影響就越大，我們推導出由寄生電阻主導的線性區轉導特性，發現推倒結果和實驗量測結果相符，證明短通道元件確實由寄生電阻主導，亦即減小寄生電阻可以有效的提升短通道元件的特性。最後，我們萃取高壓操作下，長通道元件的輸出電阻和電壓增益，和傳統的厚通道元件相比，所提出的新結構可以有相似甚至更好的表現，這使得此結構不但可以應用在低壓高速的數位電路中，也可以同時應用在高壓高增益的類比電路之中。 最後我們提出了以選擇性沉積鎢製作閘極間隙璧的複晶矽薄膜電晶體，發現元件不但可以降低汲極電場，鎢間隙壁還可以在導通狀態時於下方產生通道，減小了傳統氧化層間隙壁會使導通電流下降的缺點。另外，由於汲極電場下降的緣故，所提出的新結構可以增加元件的可靠度。不過，由於鎢金屬會擋住後續鈍化處理時的氨分子進入通道，所以當間隙壁厚道增加時，元件的鈍化效果會變差。解決方法應為在鎢間隙壁成長前先行進行鈍化處理，由於鈍化溫度和鎢沉積溫度相同，所以不必擔心鈍化效果會因為鎢沉積步驟而降低，但是後續的離子活化必須使用低溫製程，例如雷射活化，在本實驗中因為設備限制而無法驗證，期望未來可以改善之。

In this dissertation, the dimensional effects of polycrystalline silicon thin-film transistors (poly-Si TFTs) are studied. By fabricating and characterizing poly-Si TFTs with various channel geometry, different channel thickness, and different grain size. Short channel effects and narrow width effects are investigated and discussed carefully. A physically-based model describing the impact ionization effect is also established and compared with experiment results. In order to suppress the severe short channel effects of poly-Si TFTs, two kinds of novel structures are also proposed and demonstrated. They are found to exhibit better immunity to the kink effects and better performances than their conventional counterparts. Important characteristics such as parasitic effects and reliability issues of these novel poly-Si TFTs are also carefully investigated. First, we focus on studying the short channel effects of poly-Si TFTs. By extracting parameters such as threshold voltage, subthreshold swing, and field-effect mobility, typical short channel effects including threshold voltage roll-off and impact ionization effects under high electric field are discussed. The single transistor latch phenomenon is also observed in short-channel devices under high drain field, the underlying floating body mechanism and its hysteresis phenomenon can be suppressed for devices with narrow channel width. Moreover, the substrate current of devices with various channel length is measured directly from the body contact. Excluding the parasitic band-to-band tunneling current generated from the junction between inversion layer and body region, the electric-field dependent impact ionization current is observed and characterized. A physically-based model considering the vertical-field scattering effect is established to explain the behavior of impact ionization current. Good agreements are found between simulated and measured data through a wide range of gate voltage at various drain voltages. Then, the narrow channel effects are studied by using multichannel structures. The influences of side channel, RIE-induced edge defects and channel trap density are separately discussed by different groups of test devices. The RIE-induced edge defects are found to degrade devices performance when the channel width is wide. The trap density reduction with decreasing channel width, however, compensates this degradation and starts to enhance device performances when the channel width is scaled down to be comparable with the grain size. A novel poly-Si TFTs with ultrathin channel and tungsten-clad source/drain is then fabricated and demonstrated. Channel thickness of 30 nm is used to suppress the floating body effect by reducing body neutral region. To prevent the enormous parasitic source/drain resistance of ultrathin film from degrading device performances, tungsten film is deposited on the source/drain and gate regions by selectively deposition technology. The resulting parasitic resistance of proposed devices is then extracted by analyzing characteristics of devices with various channel length. It is compared with that of conventional ultrathin-channel devices and also the thick channel devices. It is found that the cladding tungsten film effectively reduce the source/drain resistance as expected. Then, a physically-based model describing the linear region transconductance including the parasitic resistance effects is derived. Simulated data are compared with measured data for devices with short channel length. Good agreements are obtained to verify the behavior of parasitic-resistance dominant transconductance as well as the parasitic-resistance dominant field effect mobility. Finally, the output resistance and voltage gain of proposed devices operated under high voltages are also investigated. Good performances are found to ensure the capability of applying the proposed TFTs on both high-speed and high-gain circuitry. Finally, a novel W-spacer short channel poly-Si TFT is fabricated. The W spacer is also formed by selectively W deposition at low temperature. No additional masks or RIE process is needed, leading to reduced production cost and less plasma damage. The spacer thickness can be controlled by changing deposition time. Generally, 600-nm-thick spacer is achievable since W deposition has a very long incubation time on oxide film. While compared with conventional TFTs, small-dimensional W-spacer TFTs have lower leakage current and comparable driving ability. This is because the LDD regions under W-spacers reduce the drain electric field and therefore lower the leakage current. When devices operated under ON state, the series resistance in the LDD region does not degrade the performance of W-spacer TFTs obviously since the W-spacer acts as a part of gate electrode to induce channel. To further study W-spacer TFTs, devices with different channel thickness, spacer thickness and LDD dopant density are fabricated and compared. It is found that W-spacer TFTs with thinner channel thickness have lower leakage current and less pronounced kink effect. This can be explained by the reduced leakage cross sectional area and smaller floating body region in thinner channel. When spacer thickness increases, the turn on current decreases slightly while the kink effect efficiently suppressed by the wider LDD region. The dopant density of LDD regions also influences the kink effect obviously. More lightly doped LDD region reduces drain electric field more efficiently. During plasma passivation process, it is also found that W film will block NH3 molecules from entering the channel region. Therefore, the passivaiton effect will be varied with different spacer thickness and various channel geometries. For devices with small dimension and thinner spacer thickness, devices exhibit better performance since they have better passivation condition. Finally, the hot-carrier reliability of W-spacer TFTs is also investigated by introducing hot-carrier stress. It is found that W-spacer TFTs have better reliability than conventional ones because they have lower drain electric field, which suppresses the impact ionization effect during hot-carrier stress.