低成本AES加密演算法的硬體設計與實現

Abstract

隨著網際網路以及各種資訊設備的快速發展，資料安全的問題也日益的受到重視。將資料加密是一般廣泛被使用的方法也是一項重要的技術。舊有的資料加密演算法已經不夠安全，於是美國NIST (National Institute of Standards and Technology)組織在2001年公開發表了一個新的加密演算法–AES (Advanced Encryption Standard)，用以取代舊有的加密演算法。然而各種新興的資訊設備不斷出現，過去光靠軟體提供加密的技術，現在則已經不敷使用，硬體化便成為一種必然的趨勢。 在此篇論文中，我們針對AES加密演算法提出了一個低成本的硬體架構。此架構能有效的降低整體晶片的面積，而資料處理量(Throughput)卻可以比同類型的設計來得更高。在TSMC 0.25μm的製程以及Synopsys Design Analyzer軟體的模擬環境下，我們的設計總共只需要15.15k個邏輯閘，並且能達到228.37Mbps的高速資料處理量。

With the rapid growth of Internet applications and various information devices, security of our data becomes an important issue. Encrypting the data is a general way to protect them, and also it is an essential technology for data security. The former encryption algorithms are not strong enough to protect data, so the US National Institute of Standards and Technology (NIST) was announced a new encryption algorithm – AES on November 26, 2001 to replace the old encryption algorithms. Now as the appearance of various information devices, software implementation of encryption algorithms in the past is insufficient, and the hardware implementation will become a trend. In this thesis, we proposed a low-cost architecture for AES. We use the ASIC design flow to implement this architecture. Using TSMC 0.25μm CMOS process technology and Synopsis Design Analyzer, our design costs 15.15k gate counts totally, and can achieve a high throughput of 228.37Mbps.