低功率壓控振盪器以及全整合化2.4GHz CMOS整數N頻率合成器設計

Abstract

本論文中提出一個作為直接降頻接收器使用的全整合化頻率合成器，工作頻率在2.45G赫茲。文中從壓控振盪器的設計開始，以低功率消耗為設計主要考量，完成一消耗功率在1毫瓦以內的壓控振盪器（若操作在1.5伏特偏壓下，僅消耗53微安培）。除頻器部分則考量電流使用量，而採用較省電的整數N組態。 頻率合成器的量測結果如下：振盪頻率可調範圍在2351~2517百萬赫茲之間，鎖定所需時間約25微秒，距主頻1百萬赫茲遠處之相位雜訊為-88.4分貝/赫茲，寄生雜頻較主頻低14分貝；使用2.5伏特電壓源時消耗功率為58.625毫瓦。

Through this thesis, we demonstrated a fully integrated frequency synthesizer for direct conversion receiver. The working frequency is at 2.45GHz. We begin from the design of voltage controlled oscillator (VCO), devising it at the purpose of low power consumption, and established a VCO consumes less than 1mW (It consumes only 53μA when biased at 1.5V VDD).In the design of frequency divider part, we adopt integer-N topology which provides a less power consumption for low current use consideration. The measurement results are listed as following: the oscillation frequency is tunable between 2351~2517MHz, locking time is approximately 25μs, phase noise is -88.4dBc/Hz@1MHz offset, spurious tones are less than carrier 14dB; the power consumption is 58.625mW using a 2.5V power supply.