適用於 5.25GHZ 互補式金氧半導體線性化功率放大器的設計

Abstract

本篇論文主旨在於使用兩種不同的補償方式來增加互補式金氧半導體功率放大器的線性度。使其適用於無線區域網路的系統。這兩個晶片的製作皆是使用標準點25微米1P5M互補式金氧半導體的製程。 在使用P通道金氧半導體補償的功率放大器晶片中‚從一個3.3V電源消耗156mA的直流電流。P通道金氧半導體補償的功率放大器晶片可以在4.5GHz的頻率下提供20.94dBm的輸出功率且有著14.2% 的汲極效率。它的輸出功率1dB壓縮點為15.2dBm‚輸出3次諧波交點為24.6dBm。使用可變電容二極體補償的功率放大器晶片有著和P通道金氧半導體補償的功率放大器晶片相同的直流電流消耗。可變電容二極體補償的功率放大器晶片可以在4.5GHz的頻率下提供21.65dBm的輸出功率且有著17% 的汲極效率。它的輸出功率1dB壓縮點為15.8dBm‚輸出3次諧波交點為26.13dBm。 在這兩種不同補償方式的功率放大器設計中‚使用可變電容二極體補償的功率放大器晶片有著較佳的線性度、效率及輸出功率。由量測的結果得知‚這兩個功率放大器晶片在接近5GHz的頻率下‚輸出功率皆大於20dBm‚最佳的輸出3次諧波交點可以超過26dBm。

Two CMOS RF power amplifiers with different compensation schemes to improve the linearity of CMOS PAs for WLAN applications are presented in this thesis. These two proposed chips are fabricated in a standard 0.25um single-poly-five-metal (1P5M) CMOS process. The proposed PMOS compensation PA consumes 156mA DC quiescent current from a 3.3V supply voltage. The two-stage PMOS compensation PA can provide up to 20.94dBm output power with 14.2% drain efficiency at 4.5GHz. The output P1dB is 15.2dBm and the output IP3 can achieve 24.6dBm. The proposed varactor compensation PA consumes the same DC quiescent current as PMOS compensation PA. The two-stage varactor compensation PA can provide up to 21.65dBm output power with 17% drain efficiency at 4.5GHz. The output P1dB is 15.8dBm and the output IP3 can achieve 26.13dBm. In these two different compensation schemes of PA designs, the varactor compensation PA has better linearity, efficiency and output power. From measured results, the performance of these two proposed CMOS RF power amplifiers have been verified to achieve output power level over 20dBm at the frequency range near 5GHz and the best output IP3 is over 26dBm.