應用在802.11a和超寬頻系統之射頻CMOS線性功率放大器之設計

Abstract

可攜式的無線通訊系統元件的市場快速成長，對建立下一代的低功率射頻積體電路產品有很大的幫助。製程的進步使的CMOS單晶片的實現越來越容易，例如IEEE 802.11a/b/g/n這樣的無線區域網路，和802.15.3a標準無線廣播服務將變的可行。 這篇論文是關於設計射頻區塊中的重要元件―功率放大器的設計。第三章，設計一疊接架構的功率放大器。此功率放大器的最大輸出功率為22dBm，功率增益為26dB，P1dB為-3dBm，在3.3V的電壓供應下總電流消耗為204mA。第四章，設計一個利用電感電阻回授的3~10GHz超寬頻功率放大器。此功率放大器在3~10GHz的範圍內，有13~0dB的功率增益，雜訊指數4~7dB。在3~6GHz的範圍內，P1db為4dBm，PAE低於3%。在1.2V的供應電壓下總功率消耗為74.4mW。 全部的結果都根據ADS的模擬和台積電0.18µm製程。量測結果為國家奈米元件實驗室(NDL)中電路量測系統的量測結果。

The rapid growth of the market for portable wireless communication devices has given great push to the development of a next generation of low power radio frequency integrated circuits (RFIC) product. A single chip CMOS transceiver has been implemented available due to improve of process, some short range wireless systems such as IEEE 802.11a/b/g/n, Wireless Local Area Network (WLAN), and the 802.15.3a standards have made wireless computing and other broadband service possible. This thesis describes the design of key RF block in the UWB transceiver- the power amplifier. In the Chapter3, a power amplifier by using cascode configuration is designed. The PA allows the maximum output power 22dBm, and has power gain 26dB, P1dB at -3dBm, and total current consumption 204mA at DC supply 3.3V. In the Chapter4, it describes a 3~10GHz power amplifier for UWB application, by use inductor-resistor feedback configuration. In practical measurement, we have power gain 13~0dB, and noise figure 4~7dB from 3~10GHz. The P1dB is 4dBm and PAE is lower than 3% from 3~6GHz. Total power consumption is 74.4mW with vg 1.2V and vd 1.2V condition. All the above mentioned results are from simulation in ADS and using TSMC 0.18µm process. The practical measurement is according to NDL RFIC measurement systems.