於 3.1-10.6GHz 無線應用的超寬頻金氧半功率放大器

Abstract

本論文以TSMC 0.18um的CMOS製程環境下，首先設計了一個兩級在3.1到10.6GHz的超寬頻功率放大器。第一級在共源、共閘的串疊結構之中，加入了電阻的迴授結構。這樣帶來了高的功率增益以及寬頻的輸入組抗匹配：而第二級利用了共源加上電阻電感迴授的結構，來達到寬頻組抗匹配以及平坦的功率增益。 接下來針對上述的功率放大器研究後，我們改進了設計的細節，進一步設計了一個3到8GHz的兩級超寬頻功率放大器。藉由將電容加入上述的迴授結構，我們減少了在迴授路徑上面的直流功率消耗。再加上對負載線設計的加強，我們在線性度以及功率轉換效益上有很大的突破。

This thesis is based on TSMC 0.18um CMOS process. A two-stage ultra-wideband CMOS power amplifier is applied for 3.1 to 10.6GHz. The 1st stage introduces the common-source and common-gate topology called “cascade” with the resistor feedback configuration. It brings higher power gain and wideband input impedance match. And the 2nd stage utilizes the common-source with resistor and inductor in order to wideband matching and power gain flatness. After further studying for the above-mentioned power amplifier, we improve the detail and design a two-stage power amplifier for 3 to 8GHz. By adding a capacitor to the feedback path, both feedback configurations at the 1st and 2nd stages decreases the DC power loss. And we obtain more suitable DC bias condition by focusing on the load-line design; it does work very much to our efficiency and linearity.