標題: | A Built-in-Self-Test I sigma-Delta ADC Prototype |
作者: | Hong, Hao-Chiao Liang, Sheng-Chuan Song, Hong-Chin 電控工程研究所 Institute of Electrical and Control Engineering |
關鍵字: | BIST;Sigma-Delta ADC;Controlled sine wave fitting;Output response analyzer |
公開日期: | 1-六月-2009 |
摘要: | This paper presents a built-in-self-test (BIST) I - pound Delta ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability I - pound Delta modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard -aEuro parts per thousand 6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications. |
URI: | http://dx.doi.org/10.1007/s10836-008-5095-x http://hdl.handle.net/11536/7167 |
ISSN: | 0923-8174 |
DOI: | 10.1007/s10836-008-5095-x |
期刊: | JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS |
Volume: | 25 |
Issue: | 2-3 |
起始頁: | 145 |
結束頁: | 156 |
顯示於類別: | 期刊論文 |