三維積體電路上減少直通矽穿孔之平行化層級感知分割演算法

Abstract

相較於傳統的二維積體電路，三維整合被視為一個具有突破性並且能夠大量提升效能的一個技術，這個新興科技的做法是垂直堆疊多層的晶片並利用直通矽穿孔來做為垂直信號的連結。雖然使用直通矽穿孔提供很多好處，但是直通矽穿孔佔用相當大的面積並且會導致可靠性的問題。基於以上我們所提到的挑戰，減少直通矽穿孔的使用量是一個很重要的問題。因此，在這篇論文中，我們提出一個兩階段的平行化層級感知的分割演算法。在第一個階段，我們使用二路最小切割演算法來得到最初的解，並且在這個階段中，我們可以藉助多核心架構來達到平行化的目的，進而減少執行時間。而在第二個階段，我們利用通用圖形處理器大量的探索模擬退火法的解空間，希望能再進一步減少直通矽穿孔數量。實驗結果顯示，相較於一些前人所提出的演算法，我們的演算法在可以減少36%的直通矽穿孔數量。

As compared to the traditional two-dimensional (2D) ICs, 3D integration is considered as a breakthrough technology which has the potential to provide significant performance and functional benefits. This emerging technology enables stacking multiple layers of dies and resolves vertical connection issue by Through-silicon vias (TSVs). However, though a lot of advantages come with using TSV, it occupies significant silicon estate and incurs reliability issue. Based on the challenges mentioned above, minimizing the number of TSVs becomes an important issue. Therefore, in this thesis, we propose a two-phase parallel layer-aware partitioning algorithm. In the first phase, 2-way min-cut partitioning is applied to get the initial solution, and the procedure can be further parallelized by multi-core. In the second phase, we improve the result using parallel simulated annealing approach on GPGPU. Experimental results show that our proposed algorithm achieves a 36% improvement on the number of TSVs as compared to several existing methods.