低功率多埠靜態隨機存取記憶體設計：寫入與讀取改善技術

Abstract

本論文針對低功率奈米級多埠靜態隨機存取記憶體設計提出討論。首先在45奈米低功率製程上，提出可改善二對埠靜態隨機存取記憶體寫入與讀取的技術。用負的寫入偏壓增進寫入能力，沒有降低另一埠的位元電流。結果顯示12%的VDDmin改善，而只增加1.9%面積。這項技術已成功的證明在65nm和45nm靜態隨機存取記憶體晶片上，在95%良率中改善了120mV的最低電壓操作。再者，我們提出一個新的多埠靜態隨機存取記憶體位元陣列架構，改善靜態雜訊限幅，增強寫入能力，減少寫讀電流消耗。我們顯示在同一列的多埠靜態隨機存取記憶體存取上，面臨了寫入干擾及讀取干擾，將在寫讀半選取的位元上引起靜態雜訊限幅減弱。這在同一列存取的半選取的位元上，也造成了較多功率消耗。因此，我們提出交叉點寫入字元線架構，減輕靜態雜訊限幅減弱。這架構跟相鄰位元分享了寫入位元線和列存取電晶體，減少了電晶體數目和面積。這架構減半寫入位元線數目，因此減少了寫入功率消耗和寫入位元線漏電。再者，我們在讀取埠堆疊上提出一個行基準的虛擬VSS 控制架構，減低讀取功率消耗。佈局後模擬顯示跟先前多埠架構相比，這推薦架構同時減少寫入讀取電流消耗超過30%。這架構使用TSMC 40奈米製程，已證明在8Kb二寫二讀多埠靜態隨機存取記憶體測試晶片上。

This dissertation discusses the write and read improvement techniques for the low-power nanoscale multi-port (MP) SRAM design. First, we present circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. Furthermore, we provide a novel structure of MP SRAM cell array to improve static noise margin (SNM), enhance write-ability, and reduce write/read current consumption. We show that the common row access on MP SRAM encounters the write-disturb or read-disturb issue which will induce the SNM degradation on write/read half-select bit-cells. The degradation of half-select bit-cells on common row access also results in more power consumption. Therefore, we present a cross-point write word-line scheme to mitigate the SNM degradation. This structure shares write bit-line and row-access transistor with adjacent bit-cells to reduce transistor count and area. This scheme can halve the write bit-line number, thus reducing write power consumption and write bit-line leakage. Moreover, we present a column-based virtual VSS control scheme on the read-port stack to reduce read power consumption. Post-sim results show that the proposed schemes reduce both write and read current consumption by over 30% compared with the previous MP structure. The proposed scheme is demonstrated and validated by an 8Kb two-write two-read MP SRAM test chip fabricated in TSMC 40 nm CMOS technology.