高介電係數閘極電晶體之負偏壓溫度不穩定性引致臨界電壓改變量分佈之統計特性和模式

Abstract

在本篇論文中，我們針對元件中個別的單電荷產生，藉由統計性的方法，探討了在高介電係數奈米級閘極電晶體元件中，負偏壓溫度不穩定性引致臨界電壓改變量之分佈。我們量測大量小面積High-k元件之單電荷產生特徵時間及其造成之臨界電壓漂移。我們發現單電荷產生之特徵時間有數decade之廣。基於RD 模型之基礎，我們提出一個統計模型，結合實驗萃取之單電荷產生之特徵時間及單電荷造成之臨界電壓漂移分佈，成功地以蒙地卡羅模擬重現實驗數據之∆Vt 分佈及其和NBTI 操作時間的關係。

In this thesis, a negative-bias-temperature-instability (NBTI) induced ∆Vt distribution is examined by a statistical study of individual trapped charge creations in nanoscale HfSiON gate dielectric pMOSFETs. We measure individual trapped charge creation times and corresponding threshold voltage shifts during NBTI stress in a large number of devices. The characteristic time distributions of the first three trapped charge creation are obtained. Wide dispersion of trap creation characteristic times in several decades is observed. A statistical model for an NBTI induced ∆Vt distribution by employing the RD model and convolving collected the trapped charge creation times and a single trapped charge induced Vt shift is developed. Our model can reproduces measurement results of an overall NBTI induced ∆Vt distribution and its stress time evolutions well.