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dc.contributor.authorChen, Jung-Shengen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:09:26Z-
dc.date.available2014-12-08T15:09:26Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0918-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/7201-
dc.identifier.urihttp://dx.doi.org/10.1109/RELPHY.2007.370002en_US
dc.description.abstractThe influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.en_US
dc.language.isoen_USen_US
dc.titleImpact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/RELPHY.2007.370002en_US
dc.identifier.journal2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUALen_US
dc.citation.spage664en_US
dc.citation.epage665en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000246989600143-
Appears in Collections:Conferences Paper


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