標題: | Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology |
作者: | Chen, Jung-Sheng Ker, Ming-Dou 電機學院 College of Electrical and Computer Engineering |
公開日期: | 2007 |
摘要: | The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter. |
URI: | http://hdl.handle.net/11536/7201 http://dx.doi.org/10.1109/RELPHY.2007.370002 |
ISBN: | 978-1-4244-0918-1 |
DOI: | 10.1109/RELPHY.2007.370002 |
期刊: | 2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL |
起始頁: | 664 |
結束頁: | 665 |
顯示於類別: | 會議論文 |