應用於離散時間三角積分調變器之校正技術

Abstract

本論文發展應用於離散時間三角積分調變器的校正技術， 藉此恢復調變器的雜訊形變能力，完成高速高解析度的類比數位轉換。 校正技術能在背景執行，不影響三角積分調變器的正常運作。 所發展的校正技術大幅放寬離散時間調變器對運算放大器電壓增益的要求， 還可以放寬串疊式調變器對濾波器匹配的要求。

寬頻的離散時間三角積分調變器,其採用的放大器必須犧牲電壓增益，以達到高速的要求。 如此導致積分器漏損的問題發生。使得三角積分調變器的解析度下降。 本論文提出解決此問題的積分器漏損校正技術。 積分器的漏損在數位端檢測，並在積分器類比端進行補償。 此技術適用於任何有積分器漏損問題的離散時間三角積分調變器。 因為運算放大器電壓增益的要求被大幅放寬，我們提出的積分器漏損校正技術 ，能在高解析度的前提下，讓離散時間調變器突破速度上限，達到高速的目標。

串疊式三角積分調變器的類比濾波器和數位雜訊消除器無法完全匹配， 其訊雜比會因為雜訊漏損問題而嚴重下滑。 本論文提出只需簡單電路便可解決此問題的雜訊漏損校正技術。 利用頻寬外的測試訊號，檢測雜訊漏損發生與否，並調整數位雜訊消除器的增益， 消彌雜訊漏損。 此技術放寬在串疊式調變器所需的匹配規格，讓調變器完成高階雜訊形變。

一個以六十五奈米金屬氧化物半導體製程實現的2-2串疊式三角積分調變器， 被用來驗證所提出的校正方法。 這調變器的每一級都由兩個含有低增益高速運算放大器的積分器所構成。 首先，積分器漏損校正技術會減少第一級的積分器漏損量， 接著，雜訊漏損校正技術會匹配類比濾波器和數位雜訊消除器。 因為這兩技術的作用，調變器得以完成高速高解析度的數位類比轉換。

實作出之串疊式調變器有效面積0.58x0.33平方釐米， 調變器採用開路增益只有十倍的運算放大器，使調變器能以每秒十一億次的時脈工作。 調變器的過取樣比率為三十三,輸入訊號頻寬為一千六百六十七萬赫茲， 供應電壓一伏特，消耗功率九十四毫瓦。 校正啟動前，訊雜比是54dB，而動態範圍是60dB。 校正啟動後，訊雜比變成74dB，而動態範圍提升到81dB。 該三角積分調變器的效能指標為163.5dB。

This thesis presents background calibration techniques to reshape the capability of noise shaping of discrete-time (DT) Delta-Sigma modulators (DSMs). The calibration can operate in the background without interrupting the normal operation of the DSM. The proposed scheme relaxes the requirement of opamp DC gain in a DT DSM. and relaxes the matching requirement in a cascaded-DSM. The opamp in a DT DSM is requested to sacrifice the DC gain for wide-band applications. This induces the issue of integrator-leakage and a degraded signal-to-noise-anddistortion ratio (SNDR). We develops an integrator-leakage calibration technique for a DT DSM. In the calibration of an integrator, its integration leakage is determined in the digital domain, and the leakage compensation is applied to the same integrator in the analog domain. The proposed scheme can be used to calibrate all of the integrators in a DT DSM of any form. The developed scheme can relax the requirement of opamp DC gain in the high-speed high-resolution DT DSMs. A cascaded DSM without the perfect matching between analog loop filters and digital noise cancellation filters exhibits a degraded SNDR due to noise leakage. We develops an noise-leakage calibration technique with low-complex circuits. The noise leakage is determined by injecting an out-of-band signal, and the leakage is eliminated by merely adjusting the gain of digital filter. The developed scheme can relax the matching requirement in the cascaded DSMs and accomplish the higher-order noise shaping. A 2-2 cascaded discrete-time DSM is fabricated in a 65 nm CMOS technology. Each stage of DSM consists of two integrators realized the low gain high speed opamp. The integrator leakage originated in the first stage is reduced by integrator leakage calibration at first. Then, the mismatch between the analog loop filter and the digital noise cancellation filter is cured by noise leakage calibration. The proposed calibrations enable the modulator to perform the high-speed high-resolution analog-to-digital conversion. The active area of the fabricated DSM is 0.58x0.33 mm2. This cascaded DSM with open-loop opamp gain of 20 dB is operating at 1.1 GHz clock rate. Its OSR is 33 and its bandwidth is 16.67 MHz. The DSM consumes 94mW from 1.0 V power supply. Before activating the calibrations, the SNDR is 54 dB and the dynamic range (DR) is 60 dB. After activating the integrator leakage calibration and the noise leakage calibration, the SNDR becomes 74 dB and the DR becomes 81 dB. The figure-of-merit of the DSM is 163.5 dB.