标题: | 应用于离散时间三角积分调变器之校正技术 Calibration Techniques for Discrete-Time Delta-Sigma Modulators |
作者: | 吴书豪 Wu, Su-Hao 吴介琮 Wu, Jieh-Tsorng 电子工程学系 电子研究所 |
关键字: | 类比数位转换器;三角积分调变器;校正技术;analog-to-digital converter;delta-sigma modulation;calibration |
公开日期: | 2012 |
摘要: | 本论文发展应用于离散时间三角积分调变器的校正技术, 藉此恢复调变器的杂讯形变能力,完成高速高解析度的类比数位转换。 校正技术能在背景执行,不影响三角积分调变器的正常运作。 所发展的校正技术大幅放宽离散时间调变器对运算放大器电压增益的要求, 还可以放宽串叠式调变器对滤波器匹配的要求。 宽频的离散时间三角积分调变器,其采用的放大器必须牺牲电压增益,以达到高速的要求。 如此导致积分器漏损的问题发生。使得三角积分调变器的解析度下降。 本论文提出解决此问题的积分器漏损校正技术。 积分器的漏损在数位端检测,并在积分器类比端进行补偿。 此技术适用于任何有积分器漏损问题的离散时间三角积分调变器。 因为运算放大器电压增益的要求被大幅放宽,我们提出的积分器漏损校正技术 ,能在高解析度的前提下,让离散时间调变器突破速度上限,达到高速的目标。 串叠式三角积分调变器的类比滤波器和数位杂讯消除器无法完全匹配, 其讯杂比会因为杂讯漏损问题而严重下滑。 本论文提出只需简单电路便可解决此问题的杂讯漏损校正技术。 利用频宽外的测试讯号,检测杂讯漏损发生与否,并调整数位杂讯消除器的增益, 消弥杂讯漏损。 此技术放宽在串叠式调变器所需的匹配规格,让调变器完成高阶杂讯形变。 一个以六十五奈米金属氧化物半导体制程实现的2-2串叠式三角积分调变器, 被用来验证所提出的校正方法。 这调变器的每一级都由两个含有低增益高速运算放大器的积分器所构成。 首先,积分器漏损校正技术会减少第一级的积分器漏损量, 接着,杂讯漏损校正技术会匹配类比滤波器和数位杂讯消除器。 因为这两技术的作用,调变器得以完成高速高解析度的数位类比转换。 实作出之串叠式调变器有效面积0.58x0.33平方厘米, 调变器采用开路增益只有十倍的运算放大器,使调变器能以每秒十一亿次的时脉工作。 调变器的过取样比率为三十三,输入讯号频宽为一千六百六十七万赫兹, 供应电压一伏特,消耗功率九十四毫瓦。 校正启动前,讯杂比是54dB,而动态范围是60dB。 校正启动后,讯杂比变成74dB,而动态范围提升到81dB。 该三角积分调变器的效能指标为163.5dB。 This thesis presents background calibration techniques to reshape the capability of noise shaping of discrete-time (DT) Delta-Sigma modulators (DSMs). The calibration can operate in the background without interrupting the normal operation of the DSM. The proposed scheme relaxes the requirement of opamp DC gain in a DT DSM. and relaxes the matching requirement in a cascaded-DSM. The opamp in a DT DSM is requested to sacrifice the DC gain for wide-band applications. This induces the issue of integrator-leakage and a degraded signal-to-noise-anddistortion ratio (SNDR). We develops an integrator-leakage calibration technique for a DT DSM. In the calibration of an integrator, its integration leakage is determined in the digital domain, and the leakage compensation is applied to the same integrator in the analog domain. The proposed scheme can be used to calibrate all of the integrators in a DT DSM of any form. The developed scheme can relax the requirement of opamp DC gain in the high-speed high-resolution DT DSMs. A cascaded DSM without the perfect matching between analog loop filters and digital noise cancellation filters exhibits a degraded SNDR due to noise leakage. We develops an noise-leakage calibration technique with low-complex circuits. The noise leakage is determined by injecting an out-of-band signal, and the leakage is eliminated by merely adjusting the gain of digital filter. The developed scheme can relax the matching requirement in the cascaded DSMs and accomplish the higher-order noise shaping. A 2-2 cascaded discrete-time DSM is fabricated in a 65 nm CMOS technology. Each stage of DSM consists of two integrators realized the low gain high speed opamp. The integrator leakage originated in the first stage is reduced by integrator leakage calibration at first. Then, the mismatch between the analog loop filter and the digital noise cancellation filter is cured by noise leakage calibration. The proposed calibrations enable the modulator to perform the high-speed high-resolution analog-to-digital conversion. The active area of the fabricated DSM is 0.58x0.33 mm2. This cascaded DSM with open-loop opamp gain of 20 dB is operating at 1.1 GHz clock rate. Its OSR is 33 and its bandwidth is 16.67 MHz. The DSM consumes 94mW from 1.0 V power supply. Before activating the calibrations, the SNDR is 54 dB and the dynamic range (DR) is 60 dB. After activating the integrator leakage calibration and the noise leakage calibration, the SNDR becomes 74 dB and the DR becomes 81 dB. The figure-of-merit of the DSM is 163.5 dB. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079311829 http://hdl.handle.net/11536/72379 |
显示于类别: | Thesis |
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