研究於鍺基板可同步之鎳(鐿)化矽之源極/汲極接面於複合金氧半場效電晶體元件之整合

Abstract

為了提高複合式金氧半電晶體的特性表現，在先進製程上已有許多發展，而其中最新且持續進行的研究就是將通道改用其他替代的材料，像是三五族和鍺元素。動機是由於矽的電洞遷移率相較於這些材料低很多，如果能藉由改變通道性質，我們可以最直接的提高電洞的遷移率，進而改善元件的表現。除了提高元件特性，降低成本也是製程上另一項重要的指標，因此，在本篇的實驗中，我們除了以鍺元素來替代矽作為基板外，我們還希望能夠矽鍺兩種基板可以進入同一道製程，這項研究的實現讓我們能以更少的製程流程來完成我們的元件，並大幅降低製程的成本。 另外蕭基特接面目前也已經是被廣泛地發展在半導體科技上，由於他接面的電性特徵與一般的p-n接面類似，除了在二極體上也有相當的應用外，我們更希望能應用在蕭基特半導體上，再利用鍺元素具有費米能階限制的效應，我們期待能以不用離子佈植的方式做出複合式金氧半電晶體，這將會是製程上非常新穎的突破。 本實驗目的即為設計出一套可以統整矽與鍺基板的元件製程流程，以達到同步進行的目的。而在我們的實驗中，我們成功的設計出一套可以整合鍺基板的金屬矽化物製程，並且退火溫度可以降低至300°C。在這套製程中，除了必須的矽或鍺原子與金屬活化所需之退火製程外，不具有其他的高溫製程，如此一來，我們可以避免一般製程所不需要的熱效應與之後的120°C的SPM清洗。藉由X-射線繞射與電子束穿透式顯微鏡的分析，讓我們能確定晶圓上的矽化物與鍺化物是存在的。

In order to improve the electric characterization performance of complex metal semiconductors, there have been a lot of developments. Among those developments, the latest and proceeding research is to replace the channel by other material such as III-V and germanium elements. The motive of the exchange is for the hole mobility of silicon is less than those materials a lot. If we could change the characteristic of channels, we could enhance the hole mobility directly, and improve the performance of devices. In addition, the other important issue is cost down of fabrications. Therefore, in this work, we not only replace the silicon substrates by germanium, but hope to realize the germanium compatible silicon fabrication. The research enables us to reduce the fabrication process flows, and significantly reduce the cost. On the other hand, schottky contact has also been well developed in semiconductor industry. It has also been widely used in diode structure for its electric behavior has similar characteristic as general p-n junction. Moreover, we hope to apply the technology on schottky FETs (Field-Effect-Transistors). And by the character of Fermi-level pinning of germanium, we look forward to produce the CMOS devices without ion implantation. That would be a vary novel breakthrough on fabrication. The purpose of this work is to design a possible integration of the element germanium compatible silicon substrate device fabrication process flows. In our experiment, we design a metal silicide process that can integrate with the Germanium substrate and the annealing temperature could downgrade to 300°C. In this process, there is no thermal fabrication except the annealing step to activate the silicon or germanium atoms with the metal. Compared to the general process, we could avoid the unwanted thermal effect and the Piranha cleaning step. By analyzing the device with the X-ray and SEM, we approved the existence of silicide and germanide.