利用高密度電漿閘極介電質於可堆疊電晶體和非揮發性記憶體

Abstract

本論文利用感應耦合型電漿化學氣相沉積系統在500℃下製備非晶矽薄膜。並使用奈秒綠光雷射尖峰使非晶矽薄膜轉換成具300nm之多晶矽薄膜。而我們透過X光繞射儀可以明顯看出結晶的波峰以及用電子束穿透顯微鏡分析驗證，此法薄膜具有大約250~350nm的結晶晶粒。此外，經由調變一氧化二氮、氬流量、射頻功率及腔體壓力等，成功開發出具高品質之超薄氧化矽和氮化矽薄膜。厚度為5nm氧化矽以及7nm氮化矽，在6百萬伏特/公分電場下，其漏電流皆小於10-8 安培/平方公分。 因此，結合此低熱預算技術及金屬閘極結構，已成功開發出具有高效能之多晶矽薄膜電晶體，其載子遷移率55 cm2/V-s、次臨界擺幅可低於0.3 V/Decade以及On/Off電流比可超過105。這項技術相當適合應用於三維積體電路元件之發展。 另外在運用此可堆疊型的薄膜電晶體，在其下方多加金屬閘極，藉由施加背電極偏壓-1V~1V時，我們可以來改變接近0.9V的電晶體的臨界電壓。藉此我們可以加入適當偏壓下，來符合不同種類邏輯電路之要求用。在低熱預算之基礎下，導入具氧化層/氮化層/ 氧化層之金屬閘極非揮發性記憶體(MONOS NVM)，可分別於16V之操作電壓下，100ns與10us進行寫入及抹除，其記憶窗口分別為1V及2V。因此具低熱預算之金屬閘極電晶體及非揮發性記憶體皆相當適合應用未來3D-ICs之垂直整合。

In this thesis, low temperature and stackable thin film transistors was presented by using novel fabrication approach. Amorphous silicon(a-Si) films was first deposited at 500℃by inductively coupled plasma chemical vapor deposition system(ICPCVD) as the BOX(buried oxide) layer. After that, the a-Si films was transformed to poly-silicon films by using nanosecond laser spike annealing. Thereafter, the crystallinity of the poly-silicon films were examined by X-Ray diffraction(XRD) and transmission electron microscope (TEM) and the grain size was found to be about 300nm. In addition, we have successfully developed high-quality ultra-thin silicon oxide and silicon nitride films through modulation of nitrous oxide, argon flow, RF power and chamber pressure, etc. The leakage current of dielectric thicknesses of both 5nm silicon nitride and 7nm silicon oxide at 6 million volts / cm electric field are less than 10-7 A / cm2 Combining the thermal budget technologies and metal gate, We have fabricated a high performance TFT that exhibits electron mobility of 55 cm2/V-s , low subthreshold swing of 0.3 V/Decade, and high on/off ratio of 105. That stacked transistors are suitable for the integration of three-dimensional integrated circuits (3D-ICs) Planar back metal gate was fabricated under the channel of TFT and we can adjust threshold voltage at about 0.9V by applying a back-gate bias from-1V to 1V. Therefore, Vth is controllable for different types of logic circuits. On the basis of low thermal budget technologies transistor, we introduce a multi-layer of oxide/nitride /oxide as MONOS nonvolatile memory (MONOS NVM). Under 16V pulse bias, this MONOS exhibits a fast program/erase speed of 100 ns and 10μs and the memory window is 1V and 1.5V. As a result, the TFT and NVMs with metal-gate fabricated by low thermal budget technologies are promising devices for the hetero-integration in 3D-ICs application.