在多核心系統中考慮動態隨機存取記憶體讀/寫特性以降低功率消耗之排程機制

Abstract

近幾年來，隨著市場及業界對於高效能、低功耗系統的需求，功耗管理的重要性已日漸增加。在現今的多核心系統當中，動態隨機存取記憶體(DRAM)的功率消耗佔了整個系統的一大部分，因此吸引了許多人研究DRAM的功耗管理。而除了功率消耗之外，DRAM同時還是目前多核心系統中的效能瓶頸，所以在設計DRAM功耗管理的方法時，必須格外地小心以避免大幅度地降低系統效能。目前關於DRAM功耗管理方法的研究中，有大量的研究是透過DRAM的排程機制來排序指令以降低功率消耗。在此基礎上，本篇論文提出考慮DRAM讀/寫特性的指令調節技術以及指令排程機制，在不影響系統效能的前提下，進一步降低DRAM功率消耗。根據實驗結果，本篇論文提出的機制平均能夠有效降低75%的DRAM功率消耗。若與現有的方法比較，本篇論文所提出的機制能夠在相同甚至是較少的系統效能損失之下，多降低10%的DRAM功率消耗。

The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption. Moreover, the performance of nowadays system is limited by the memory wall, which implies that a careless DRAM power management policy may harm the system performance dramatically. Among all the DRAM power management policies, reordering based DRAM scheduling has been widely studied to reduce the power. To further reduce the power while preserving the system performance, this thesis proposes the read-write aware throttling and the read-write reordering techniques. The proposed techniques effectively reduce 75% DRAM power on average. When compared to the existing work, the proposed techniques reduce 10% more power with comparable or less performance degradation on average.