标题: | 非挥发性快闪记忆体新式写入序列方法之研究 Development of the new programming sequence for non-volatile Flash memory |
作者: | 毛妮娜 Mitiukhina Nina 白田理一郎 Shirota Riichiro 电机资讯国际学程 |
关键字: | 快闪记忆体;写入序列方法;耐久力;可靠性;NAND Flash;Write operation;Endurance;Reliability study |
公开日期: | 2012 |
摘要: | 由于过去几十年来NAND型快闪记忆体生产成本的持续下降,NAND快闪记忆体已被广泛的使用在目前各式的消费型电子产品中。因为它采用串联的架构,NAND型快闪记忆体相当适合制程上的微缩,此外每个记忆体单元可储存的资讯量还可达到四个位元的大小(多位准型单元)。除了可以提供高集成密度的记忆容量之外,它还有极佳的耐冲电阻(Shock Resistance)及低功率损耗的特性。 不过NAND快闪记忆体也有几个常见的缺点,如高位元错误率(Bit Error Rate) 还有为了维持产量而容易在制造过程中产生坏轨区(Bad Blocks),以及较差的重复使用率。 在原本NAND型快闪记忆体的架构中,写入及抹除的过程是采用福勒-诺德汉穿隧效应(Fowler-Nordheim tunneling)来达成。采用此种架构,我们可以有较小的写入电流,但是所需偏压却相当高(高达二十伏特),因此,对于接面处的氧化层会造成相当的伤害,进而造成元件可靠度与性能的下降。 在此篇论文中,我们提出了一种新颖的写入序列架构,不但维持了低功率损耗的特性也降低了使用偏压的位准。我们使用了三维的数值模拟与实际的量测来分析,使用的样品为46奈米制程的记忆体阵列。根据我们的研究成果,我们成功降低了三倍以上的写入电场,另外我们亦分析了新旧方法之写入速度、临限电压分布与各种不同写入杂讯的特性比较。 Due to its continuous cost reduction through last several decades, NAND Flash has been widely adopted in consumer electronics. NAND Flash is well-suited for scaling due to its unique cell-in-series architecture; moreover, each cell can store up to 4bits of information (Multi Level Cell array). Aside offering the ultra-high-density storage capacity, this memory possesses excellent shock resistance and is characterized with lower-power operation. Disadvantages of the NAND Flash include high bit error rate, presence of number of the bad blocks due to manufacturing yield constraints and chip wearing over the time. In the several years after architecture emerged, Fowler-Nordheim tunneling has been utilized to program and erase NAND Flash cell. While consuming a low program string current, it requires very high voltages (up to 20V), causing a large stress to interface oxide, degrading the device reliability and performance. In this work the novel low-voltage low-power NAND Flash programming sequence is presented. Study was carried out with the help of 3D numerical simulations and in situ measurements. The research workbench included the 46nm-node 128 BL 32bit string mini-array. As result of this research, programming stress reduction up to 3 times was achieved. Programming speed, memory window and various types of program disturb were investigated and compared against the traditional program operation. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT070060805 http://hdl.handle.net/11536/72771 |
显示于类别: | Thesis |