高深寬比TSV填銅製程與熱機械應力特性研究

Abstract

為了解決在2D IC技術的瓶頸，IC製造產業已從2D平面製造技術轉向3D IC製造技術，因此3D IC構裝技術已被認為是新一世代半導體構裝新技術，而3D IC最大特點在於可讓不同矽晶片基板，利用矽穿孔(Through Silicon Via；TSV)技術進行立體堆疊整合，不但可縮短金屬導線長度及連線電阻，也能進一步減少晶片面積。利用銅填充穿越矽晶片的通孔是實現3D IC的決定性因素之一；沈積晶種層與隨後的電鍍充填，已經成為標準的TSV製程。為了完成無空隙的金屬充填，後續製程的晶種層的特性及電鍍製程之化學參數都必須達到最佳化，以便加速沈積效率，完成由下而上的金屬填充。想要以電鍍的方式製作高深寬比的銅填孔製程，必須在電鍍液添加適當的添加劑，以便於通孔內產生superfilling的現象，才能達到金屬化且無孔洞的填孔製程。

本論文主要探討在高深寬比TSV填銅製程時，鍍液的添加劑(包括加速劑,抑制劑,平整劑)在通孔電鍍中所扮演的角色及功能，並證實須在三種添加劑同時存在下，才能完成superfilling的填孔製程，並用於深寬比10:1的通孔填孔上；接著選用填孔完成的高深寬比(AR≧ 3：1)通孔晶片，再經過不同溫度(100℃~500℃)的熱處理，由於矽與銅的熱膨脹係數差異大，由實驗中發現當TSV銅柱經過300℃以上之高溫處理後，會發生明顯的銅金屬突出(Copper Protrusion )的現象，且因孔內銅金屬膨脹之應變(stress strain)現象使得矽晶圓產生龜裂，且裂縫方向沿著<110> 方向之銅柱與銅柱之最短距離產生連續性的破裂。隨著熱處理溫度越高，矽表面所產的裂縫越大且TSV銅柱表面的Ra及Rt也同步升高。由x-ray檢測上可發現在400℃以上已有些許銅擴散現象，尤其以500℃以上觀察到銅擴散的現象尤其明顯。因此未來如能適度的改善TSV銅生長幾何結構及無孔隙的填孔技術可減緩crack driving force，降低孔內銅金屬銅突出(Copper Protrusion)的狀況，除了提升IC元件可靠性之外，亦會降低後續CMP製程之風險及成本。

To solve the bottleneck of 2D-IC technique, IC manufacturing industry of 2D planar will turn into 3D IC fabrication. Hence, 3D IC packaging technology has already regarded as the next-generation semiconductor technology. The main characteristic of 3D IC is to use the through-silicon via (TSV) technology for stacking integration at the different silicon substrates.It not only decreases the metal-wire length and contact-line resistance, but also can decrease the chip area further. One of the determined factors for performing 3D IC is to use a process of copper via filling and through silcon via. The deposited seed layer and subsequent electroplating for filling have already become a standard TSV process. To achieve the gapless metal filling, the characteristic of seed layer and chemical parameters of electroplating process must gain the optimization that can increase the deposited efficiency and perform the bottom-up metal filling.If the high aspect ratio TSV via are made by means of electroplating , several proper organic additives must be added into the plating solution. This can result in the superfilling phenomenon and thereupon obtain void-free and via filling results

Firstly, this thesis focuses on the role and the function played by the additives including accelerators, suppressor, leveling agents in the through-hole plating of the high aspect ratio TSV copper filling process. Next, it verified that the superfilling process applied to deep hole filling with a10:1 aspect ratio can only be completed when three additives are simultaneously present in the plating bath. Then, the phenomenon of copper protrusion and silicon wafer cracks happened on wafers with high aspect ratio (AR ≧ 3:1) through-hole structures after treating in different high temperatures (100 ℃ ~ 500 ℃) because of the large thermal expansion differences between silicon and copper. The experiment found that when the TSV pillars after a heat treatment above 300 ℃ will occur a significant copper protrusion phenomenon. And due to the thermal expansion stress strain of copper metal in holes, the continuous fractures happened along the <110> direction and the shortest distance of the pillars. The higher heat treatment temperature was applied, the larger width of silicon surface cracks and the bigger Ra and Rt on top TSV copper pillar surface were measured. Under the x-ray detector examined we also found a little copper diffusion phenomenon observed on wafers treated by heat above 400 ℃, especially in cases treated above 500 ℃ . Consequently, this futher study reasonably improves TSV Cu-gained geometric structures and gapless for filling technology, which can retard the crack driving force, and reduce the copper protrusion conditions from the copper metal of the inner hole. In addition, it can not only increase IC devices reliability, but can reduce the risky and the cost in following-up CMP process.