標題: Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme
作者: Chiang, Cheng-Hao
Kuo, Li-Min
Hu, Yu-Chen
Huang, Wen-Chun
Ko, Cheng-Ta
Chen, Kuan-Neng
電子物理學系
電子工程學系及電子研究所
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
關鍵字: 3-D integration;bottom-up plating;through-silicon via (TSV)
公開日期: 1-五月-2013
摘要: A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.
URI: http://dx.doi.org/10.1109/LED.2013.2250249
http://hdl.handle.net/11536/21908
ISSN: 0741-3106
DOI: 10.1109/LED.2013.2250249
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 34
Issue: 5
起始頁: 671
結束頁: 673
顯示於類別:期刊論文


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