考慮溫度效應影響的統計型軟性電子錯誤率分析架構

Abstract

奈米級CMOS 電路設計的可靠度分析中，軟性電子錯誤率被視為重要的議題之一。在篇論文中，45nm 製程下的電路c17 (ISCAS’85)的軟性電子錯誤率隨著溫度的變化在本文中第一次被分析。實驗結果發現當溫度由25°C 上升至125°C，軟性電子錯誤率增加超過2 倍。因此，我們提出了一種考慮溫度效應影響下的統計型軟性電子錯誤率分析架構，能夠準確且快速地計算出電路的軟性電子錯誤率，並且同時考慮製程的變異以及溫度效應。藉由實驗結果發現，我們的架構與蒙地卡羅SPICE 模擬相比，達到加速的效果，並實現了高精確度的估計（<4％的誤差）。

Soft error has become one of the most critical reliability issues for nano-scaled CMOS designs. Many previous works discovered that the pulse width due to a particle strike on the device increases with temperature, but its chip-level effect has not yet been investigated with soft-error-rate (SER). Therefore, in this paper, a combinational circuit (c17 from ISCAS‘85) using a 45nm CMOS technology is first observed under different temperatures for SER. As a result, a SER increase (2X more) is found on c17 as the ambient temperature elevates from 25 °C to 125 °C. Second, along with growing design complexity, the operational temperatures of gates are distributed in a wide range and can be 2 to 3 times higher than the ambient temperature in reality. Therefore, we are motivated to build a temperature-aware SSER analysis framework (TASSER) that integrates statistical cell modeling to consider the ambient temperature (Ta) and the temperature variation (Tv), simultaneously. Experimental result shows that our SER analysis framework is highly efficient (with four-order speed-ups) and accurate (with only <4% errors), when compared with Monte-Carlo SPICE simulation.