封裝佈局上基於電源完整性且有效率成本導向之去耦合電容最佳化

Abstract

在基於電源完整性考量下的電源分配網路設計中，確保能提供穩定電壓至 晶片上的元件是非常重要的。而普遍來說都是藉由放置去耦合電容(Decoupling Capacitor)來抑制元件的切換雜訊。目前已有多篇著作探討如何基於電源完整性考量去選擇最佳的去耦合電容組合給晶片、封裝、印刷電路板，但其所挑選出的去耦合電容基於成本以及可製造性的考量，很難應用於實際設計中。我們提出了一個有效率的演算法名為“優先去耦合電容選擇的粒子群聚演算法”來自動化且最佳化地選擇去耦合電容組合。其利用粒子群聚演算法隨機搜尋的優點且優先採用較為有效的去耦合電容。我們應用此演算法到三個實際業界的封裝設計中，而結果顯示與工程師根據經驗法則所選出的去耦合電容相比，我們的演算法能基於同樣甚至更低的成本中選出更好的組合，並縮短設計時程。我們的演算法亦能同時考慮晶片、封裝、印刷電路板的共同設計在不同的操作頻率下做最佳化。

In designing reliable power distribution networks (PDN) for power integrity (PI), it is essential to stabilize voltage supply to devices on chip. We usually employ decoupling capacitor (decap) to suppress the noise generated by the switching of devices. There have been numerous prior works on how to select/insert decaps in chip, package, or board to maintain PI, however optimal decap selection is usually not applicable due to design budget and manufacturability. Moreover, design cost is seldom touched or mentioned. In this research, we propose an efficient methodology “PDC-PSO” to automatically optimizing the selection of available decaps. This algorithm not only takes advantage of particle swarm optimization (PSO) to stochastically search the design space, but takes the most effective range of decaps into consideration to outperform the basic PSO. We apply this to three real package designs and the results show that, compared to the original decap selection by rules of thumb, our approach could shorten the design period and we have better combination of decaps at the same or lower cost. In addition, our methodology can also consider package-board co-design in optimizing different operation frequencies.