低耗電的位址匯流排編碼方法

Abstract

近年來如何降低電腦系統中的耗電量已經是個非常重要的課題了。一般而言，系統中耗用在連接處理器與記憶體之間匯流排上的電量高達50%以上，這些電能是被傳送資料時各個匯流排線路產生的電位變化所消耗掉的，因此藉由資料編碼/解碼方法減少匯流排線路產生的電位變化就成了降低匯流排耗電量最有效的方法。在此，我針對指令位址匯流排、資料位址匯流排，以及混和指令/資料位址匯流排分別設計了編碼機制，來減少匯流排上產生的電位變化，以減少其上的電能消耗。對於指令位址匯流排，設計了DAT (Discontinuous Address Table)與T0搭配，以同時處理連續位址以及branch指令造成的不連續位址；對於資料位址匯流排，設計了一方法，其中結合T0與BI、動態改變位址跨距(Stride)，以及區別讀/寫位址分別編碼，可因應資料位址中連續位址與不連續位址混雜的特性來做處理；對於混和指令/資料位址匯流排，利用了指令記憶體位址與資料記憶體位址之間的關係，設計了Stride Table方法，並與DAT搭配，作為此環境的編碼設計。實驗結果顯示，這樣的方法能夠減少指令位址匯流排上90.5%的電位變化、資料位址匯流排上26%的電位變化、以及混和指令/資料位址匯流排上77.4%的電位變化。

Reducing power consumption of computer systems has gained much research attention recently. In a typical system, the memory bus power constitute will over 50% of all system power; and this power is required due to bus signal transitions (0->1 or 1->0). Reducing the number of memory bus transitions is hence an effective way to reduce system power. I present encoding schemes to reduce instruction address bus, data address bus, and instruction/data mixed address bus power consumption. For instruction address bus, T0 with DAT (Discontinuous Address Table) is proposed to handle both consecutive addresses and the branch target addresses; for data address bus, combination of T0 and BI method, variable-stride, and SRWEC (Separated Read/Write Encoding Contents) is proposed to handle both the randomness and continuities of data address sequence; as for instruction/data mixed address bus, DAT is used for instruction address sequence and Stride-Table which can take use of the relationship between instruction address and data address is applied for data address sequence. Simulation results show that the overall bus line switching reduction is 90.5% of unencoded instruction address bus, 26% of unencoded data address bus, and 77.4% of unencoded instruction/data mixed address bus.