使用SMT表面黏著技術評估銅柱凸塊覆晶元件封裝之研究

Abstract

覆晶封裝技術是指在晶圓上完成凸塊製程後將晶圓切割成單顆晶粒，再透過覆晶銲接機將晶粒與IC 載板進行接合，之後透過迴銲製程完成封裝元件的固定。此新的封裝型態符合電子元件市場上的高功能、高可靠度和低價位的技術需求。早期凸塊製程是以錫鉛凸塊或是錫銀銅凸塊為主，但隨著晶圓製程的微縮，晶粒尺寸的縮小，錫鉛凸塊或是錫銀銅凸塊已無法符合新一代技術需求，因此，能符合小間距的銅柱凸塊漸漸獲得重視。 為增加覆晶製程的彈性配置以及與系統化構件(SIP)、2.5D IC…等新型態封裝構件快速整合的作業需求，本研究評估使用表面黏著技術在相同銅柱凸塊覆晶條件下，搭配不同成份之錫膏、導線架材料將晶粒與IC 載板進行接合並預期逹到高可靠度的需求。透過銲接製程參數的調整、最佳化後進行可靠度與加速壽命試驗。將測試結果分析確認符合韋布分布後計算出相關參數並使用Arrhenius relationship公式預測產品使用壽命。 研究發現搭配表面黏著技術搭配三種不同成份的錫膏-① 錫96.5%/銀3%銅/0.5%、② 錫97%/銀3%/與 ③ 錫95.5%/銀4%/銅0.5% ，在純銅表面處理的導線架基板上可以達到10年以上的使用壽命並符合電子元件在可靠性上的需求，其中，以相同製程搭配錫95.5%/銀4%/銅0.5% 的錫膏可以得到最好的可靠性結果。

Flip chip assembly technology means to deposit bumps on the chip pads on the topside of a wafer, the second step is to saw the wafer into chip units and use flip chip bonder to mount chips on carriers like substrates or lead frames. The final step is to use IR reflow oven to firm the package. Solder bump technology has been developed in the beginning of flip chip package technology and has high volume production today, but now the copper pillar bump trends up due to the process limit of solder bump. To meet the high flexible operation in flip chip process and integrate with other packages such as System in Package (SiP), 2.5D IC…etc, we investigate surface mount technology (SMT) and daisy-chain chip with copper pillar bump in this study. The materials are also considered for different components of solder paste and lead frame surface treatment. After process optimization, the samples proceed reliability test and Accelerated Lifetime Test (AL). After confirmed the data can meet Weibull distribution, we use Arrhenius relationship equation to predict the use lifetime. Finally, we found the SMT process with 3 types of solder pastes (Sn 96.5%/ Ag 3%/ Cu 0.5%, Sn 97%/ Ag 3%, Sn 95.5%/ Ag 4%/ Cu 0.5%) and pure copper treatment on lead frame surface can reach use lifetime and high reliability requirement for ten years, the best result for the reliability performance is the same process with Sn 95.5%/ Ag 4%/ Cu 0.5% solder paste.