在雙模OFDM和DSSS無線網路下低取樣率之封包同步器的設計與分析

Abstract

在現代無線通訊系統中，直接序列展頻(DSSS)和正交頻率多重分割(OFDM)被廣泛的使用。有越來越多現實中的系統和規格，例如IEEE 802.11g，將這兩種調變整合到同一個作業平台上。然而，不同的調變方式所佔據頻□不同，導致需要兩套不同取樣頻率的類比/數位轉換器(ADC)，來達成偵測和同步所收到的訊號。 在這份論文中，將架構以IEEE 802.11g為基準的參考平台。首先提出的接收器架構，只包括一套類比/數位轉換器和動態取樣來降低硬體成本。全數位鎖相迴路(ADPLL)所動態提供的取樣頻率和相位可由基頻處理器(base band processor)來控制，以達成最佳的符號時序(symbol timing)。接下來，在DSSS/OFDM共存系統中的封包偵測(packet detection) 演算法，以及OFDM符號時序估計演算法將被展現。並且分析封包漏失 (packet loss)和錯誤宣告(false alarm)的機率。最後，以．13微米的製程實作一顆晶片，以驗証其可行性。

Direct Sequence Spreading Spectrum (DSSS) and Orthogonal Frequency Division Multiplexing (OFDM) are widely used in modern wireless communications systems. There are more and more practical systems and standards, such as IEEE 802.11g, integrating these two modulation schemes into one operating platform. Different modulation systems, however, occupy different bandwidth, whereas two sets of ADCs with two sampling rate have to be used to detect and synchronize the received signals. In this thesis, a reference design based on IEEE 802.11g is constructed. First, the proposed receiver architecture consists of only one set of ADCs with dynamic sampling in order to reduce hardware cost. The sampling frequency and phase from ADPLL can be controlled by the base band processor and thus approaches the optimum symbol timing. Furthermore, a packet detection algorithm for the coexistence of DSSS/OFDM system, and an algorithm for OFDM symbol timing estimation are presented. The probabilities of packet loss and false alarm are analyzed. Finally, a test chip using 0.13 um technology is implemented to verify the feasibility.