考慮時序效應三維積體電路平面規劃

Abstract

隨著VLSI技術日益的進步，半導體製程的進步似乎無法再符合摩爾定律。因此， 三維積體電路的概念被提出，並用以延續摩爾定律的壽命。三維積體電路是由堆 疊數層的二維積體電路而成，並在層與層之間導入了矽穿孔 (TSV)，以溝通各層 間訊號。在本論文中，我們提出了一個考慮時序效應的三維積體電路平面規劃， 用以解決時序違反。我們採用了兩階段的時序分析。在第一階段中，採用簡單且 快速的查表法。在第二階段中，一個高精確度的方式被使用。經由該方法，我們 可以提供一組可靠的答案給下一階段的實體化設計。實驗結果顯示，相較於最短 線長法，我們所提出的方法可以有效的改進最差的時序。

The improvement in the semiconductor technology seems unable to maintain the Moore’s law. Therefore, three-dimensional (3-D) IC is imported to extend this limit. 3-D IC is to stack several 2-D ICs and use through silicon via (TSV) as iter-layer connection. In this thesis, a timing-driven 3-D floorplanner is proposed, and a two-stage timing analysis method is applied to estimate circuit delay. In the first stage, a simple yet efficient look-up table method is adopted, while an accurate timing analysis algorithm is used in second stage. The proposed method can provide a reliable floorplanning result for later steps in physical design flow. Comparing with traditional min-wirelength floorplanner, the proposed algorithm can improve timing slack a lot. ii