適用於HEVC之高輸出率CABAC編解碼器設計

Abstract

這篇論文提供了一個高輸出率CABAC編解碼器設計，適用於HEVC編碼標準。編解碼器提供了高輸出率來滿足越大的畫面以及越高的每秒幀數。 我們提出的編碼設計，採用了並行和可以擴展輸出量的二進制算術編碼機制，細項有下列3個：前瞻的邊界更新、索引選擇的範圍更新和前文的分組方法。這些能移除關鍵路徑的限制，轉換成並行化的流程，以提高輸出率。利用台積電半導體 90nm的技術合成電路，操作在時鐘頻率270MHz下，能提供每秒1.8G位元的輸出率，而硬體則需要101,226個邏輯閘。 在解碼架構上，使用了並行化的語法元素分析器來達到高輸出率的多符號解碼設計，傳統設計則是使用基於預測機制的多符號解碼設計，而且會造成相依性的問題，我們所提出的架構則可以利用選擇的方式解決相依性的問題。硬體實作提供了兩個版本，利用台積電半導體，操作在時鐘頻率270MHz下，能夠每個時鐘週期產生一個位元的解碼和48,430個邏輯閘，而每個時鐘週期產生三個位元的解碼需要209,422個邏輯閘。

This thesis proposes a high throughput Context Adaptive Binary Arithmetic Coding (CABAC) codec for High Efficiency Video Coding (HEVC). The codec provides the high throughput architecture to meet the large video frame size and high frame rate requirement. The proposed encoder design adopts a parallel and throughput scalable binary arithmetic machine with lookahead low update, index select range update and context model grouping method. The proposed approach removes the longer critical path limit for higher throughput by transforming the dependency problem to be parallel one. The implementation with TSMC 90nm CMOS technology can process 1.8G bins per second in average (Level 6.2) with 101,226 gate count when operating at 270MHz. The decoder design achieves constant high throughput multi-bin decoding with the parallel syntax element parser to solve the dependency problem in the traditional prediction based multi-bin architecture. The two version of implementation with TSMC 90nm CMOS technology can process 1 bins per cycles with 48,430 gate count (270Mbins/sec, Level 5.1) or 3 bins per cycle with 209,422 gate count (810Mbins/sec, Level 6.1) when operating at 270MHz.