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dc.contributor.authorShih, Che-Huaen_US
dc.contributor.authorHuang, Juinn-Daren_US
dc.contributor.authorJon, Jing-Yangen_US
dc.date.accessioned2014-12-08T15:09:35Z-
dc.date.available2014-12-08T15:09:35Z-
dc.date.issued2009-05-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2008.2006042en_US
dc.identifier.urihttp://hdl.handle.net/11536/7333-
dc.description.abstractVerifying if an integrated component is compliant with certain interface protocol is a vital issue in component-based system-on-a-chip (SoC) designs. For simulation-based verification, generating massive constrained simulation stimuli is becoming crucial to achieve a high verification quality. To further improve the quality, stimulus biasing techniques are often used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the non-deterministic extended finite-state machine (NEFSM), and then propose an automatic stimulus generation. approach based on it. This approach is capable of providing numerous biasing strategies. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.en_US
dc.language.isoen_USen_US
dc.subjectDesign automationen_US
dc.subjectgeneratorsen_US
dc.titleAutomatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSMen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2008.2006042en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume17en_US
dc.citation.issue5en_US
dc.citation.spage723en_US
dc.citation.epage727en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000265457700012-
dc.citation.woscount0-
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