具製程、溫度感測器之熱效能管理應用在矽穿孔三維整合

Abstract

在矽穿孔三維積體電路(TSV 3D-ICs)中，堆疊多層矽晶體電路將會面臨熱應力以及臨界電壓漂移的問題。本論文提出了一個應用在矽穿孔三維整合電路之熱控管機制，利用熱傳導保護環以及熱傳導矽穿孔，將三維整合電路切割成數個熱域，能有效降低電路上的溫度；此外，在各個熱域當中，利用可解析熱傳導模型，即能計算出熱域中熱點和熱傳導保護環之間的偏移溫度，並利用本論文提出的製成-溫度感測器，可同時偵測電晶體效能飄移及熱傳導保護環溫度，進而推算出熱域中熱點溫度。模擬結果顯示，透過熱傳導矽穿孔以及熱傳導保護環之熱控管機制，能使得平均溫度下降21ºC。此外，製成及溫度的資訊是藉由對製成敏感且溫度相關的震盪器所解調出，本論文所提出的感測器是基於台積電65奈米低能耗製程，每次感測之電量消耗為430.8pJ且面積佔1591μm2，而Vthn, Vthp的感測度及溫度不準確度分跌為±1.2mV, ±0.7mV及±2.2C。

In TSV (through-silicon-via) 3D integrations, stacking multiple dies would face a severe challenge of the thermal stress and Vt scatter. In this thesis, a thermal management with an in-situ self-calibrated process-temperature (PT) sensor for TSV 3D-ICs is proposed using thermal guard rings and thermal TSVs to decrease temperature. Depending on the thermal guard ring and thermal TSVs, an analytical model for on-chip heat dissipation in each power-thermal domain is also presented in this thesis to calculate the offset temperatures between the hotspots in the power-thermal domain and thermal guard ring. The simulation results show the thermal control mechanism can achieve average temperature reduction by 21ºC via the thermal guard rings and thermal TSV. Additionally, the PT sensor is designed to monitor the transistor variations (Vtn, Vtp) and temperature for TSV 3D integrations. Also, the process information and temperature can be decoupled using the process-sensitive and temperature-dependent ring oscillators. The proposed PT sensor can realize 430.8pJ per conversion and 1591μm2 area occupation, and the sensitivities of Vthn, Vthp and the inaccuracy of temperature are merely ±1.2mV, ±0.7mV, and ±2.2C based on TSMC 65nm LP process after fabrication.