全數位快速鎖定且具可程式工作週期之脈寬調變電路

Abstract

在數位系統中，時脈訊號常被用來用於同步系統中不同部分的信號，為了符合能在單晶片系統中達到高速訊號處理的要求，雙資料速率技術常被使用以符合需求，像是雙資料速率記憶體以及高速動態電路。雙資料速率技術同時使用參考訊號的上升及下降緣來取樣信號以降低整體電路的操作速度，並且通常取樣脈波需要精準的50%工作週期。因為在製程、電壓、以及溫度變異之下，輸出訊號的工作週期會被影響，這些差異會在系統運作上會產生嚴重的問題，所以如何產生精準的50%工作週期相當的重要。此外，在某些應用中，如一些特殊的導管式類比數位轉換器及數位類比轉換器，需要可程式化工作週期比之輸入訊號。 本論文提出兩個全數位脈寬調變電路來達成可程式化工作週期之輸出脈波。第一個電路為全速位快速鎖定脈寬調變電路具可程式化工作週期，與現有技術比較，我們使用兩組延遲序列和一個時間數位偵測器讓脈寬調變電路可以操作在很寬的頻率範圍內，用較少的延遲單元，同時保持相同的精準度。所提出之工作週期設定電路可以計算出所需工作週期之輸出脈波，而不需要而外的對照表。量測台積電0.18微米CMOS 技術之脈寬調變電路，顯示此電路可操作頻率範圍為200MHz到600MHz，可輸入訊號之工作週期範圍為30%到70%，可輸出脈波之工作週期範圍為31.25%到68.75%，間距為6.25%。 第二個電路提出一個20MHz到900MHz全數位脈寬調變電路使用8階多工器延遲單元之環狀微刻度時間數位轉換器。8階多工器延遲單元之環狀微刻度時間數位轉換器會先偵測輸入脈波的週期然後根據所需的工作週期算出所需延遲時間來產生我們需要的輸出脈波。同時使用預先處理邏輯以及計數冗餘校正器，可以加速偵測時間以及校正時間數位轉換器中計數器所產生的計數錯誤。量測台積電90奈米CMOS 技術之脈寬調變電路，顯示此電路在1V供應電壓及輸出頻率為900MHz時功率消耗為1.32微瓦，可輸出脈波之工作週期範圍為31.25%到68.75%，間距為6.25%。量測之均方根以及峰對峰jitter值分別為4.539ps以及25ps，可操作頻率為20MHz到900MHz。

In digital systems, a clock is required to synchronize different parts of signals. In order to meet the requirements of the high-speed operation for SOC systems, double data rate (DDR) technology is often used to achieve the need, such as DDR-SDRAM and high speed dynamic circuits. The DDR technology uses both the rising and falling edges of the reference clock to sample the signal for reducing the operation frequency, and the clock requires a precise 50% duty cycle. Since process, voltage, and temperature (PVT) may influence the duty cycle of the clock signal, the variation of the clock duty cycle may cause serious errors in system operation. Therefore, how to generate a clock with precise 50% duty-cycle becomes very significant. Furthermore, some applications, like some special pipeline analog-to- digital/digital-to-analog converters (ADC/DAC), require an input clock with programmable duty cycles. In this dissertation, we propose two pulsewidth controlled circuits to obtain output clocks with programmable duty cycles. The first one is an all-digital fast-locking pulsewidth-control circuit with programmable duty-cycle. In comparison with prior art, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This study presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. The circuit was fabricated under the TSMC 0.18-µm CMOS process. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600MHz, and an input duty cycle ranging from 30 to 70%. It achieves a programmable output duty cycle ranging from 31.25 to 68.75% in increments of 6.25%. The second one is a 20-900 MHz all-digital duty cycle programmable circuit using 8-Stage MUX-based cyclic Vernier ring time-to-digital converter. The 8-stage MB-CVRTDC is used to detect the period of the input clock and then calculate the corresponding delay to generate the output clock with the desired duty cycle. With both the pre-logic unit and counter redundancy corrector (CRC), the detected time can be decrease and the counting error of the counters used in the TDC can be corrected. The circuit was fabricated by the TSMC 90nm CMOS process. The total power consumption for the entire duty cycle programmable circuit is only 1.32mW at 900MHz with 1V supply, while producing a programmable duty-cycle output ranged from 31.25 to 68.75% in increments of 6.25% with a wide frequency operation range from 20 to 900MHz.