一種帶通採樣抖動減噪接收器以及硬體實現

Abstract

In this thesis, we investigate the performance of a band-pass sampling OFDM receiver and propose a new low-cost way to mitigate the effect of sampling uncertainty. Signal analysis and simulation results are provided for the proposed system. We observe the measurement result that proposed system can reduce the effect of sampling uncertainty. Besides, several hardware units are dedicated designs for the implementation. We implement the ADC PCB board for sampling RF signal and the proposed system is designed in a low-cost FPGA chip and can use a clock rate of 140MHz.

In this thesis, we investigate the performance of a band-pass sampling OFDM receiver and propose a new low-cost way to mitigate the effect of sampling uncertainty. Signal analysis and simulation results are provided for the proposed system. We observe the measurement result that proposed system can reduce the effect of sampling uncertainty. Besides, several hardware units are dedicated designs for the implementation. We implement the ADC PCB board for sampling RF signal and the proposed system is designed in a low-cost FPGA chip and can use a clock rate of 140MHz.