原子層沉積二氧化鋯/三氧化二鋁於砷化銦鎵金氧半電容之電性與表面化性分析的研究

Abstract

在此篇論文初，我們研究了利用原子層沉積系統的前驅物做表面的預處理，像是TMA 以及 TEMAZ。然而，與TEMAZ 相比，我們發現TMA 表面處理可以有效地抑制聚積區的頻率分散與空乏區的介面缺陷電荷。為了更進一步探討二氧化鋯/砷化銦鎵的介面與閘極氧化層的特性，我們使用了不同的後沉積退火溫度及氮氫混合氣體退火。此外，藉由TMA 預處理，我們在二氧化鋯與砷化銦鎵的介面併入數層的三氧化二鋁，並且討論其表面特性。從數據分析上指出電容在每個不同的三氧化二鋁層條件下，後沉積退火溫度300度及氮氫混合氣體退火展現最好的電性。另外，我們利用電導法來萃取介面缺陷電荷密度;仍然可以觀察到在PDA 溫度300度及FGA下能隙深處 (midgap) 的缺陷電荷是最低的。在XPS分析的證明下，我們推測這個結果可能是在電容介面上有較高的As2+/As2O5、As2O3/As2O5、In2O3/InAsO4。此外，從電性與表面化學特性來看，我們可以證實較厚的三氧化二鋁夾層可以改善介面品質。 最後，我們建立了一個分佈模型來解釋操作在聚積區之半導體表面與閘極氧化層內缺陷的穿隧機制。然後我們利用模型與實驗數據做媒合並且定量地萃取閘極介電層內的缺陷密度。而與前面的結果相比有很好的一致性。

In the beginning of this thesis, we have investigated the surface pretreatment before depositing gate dielectric by using the precursors of ALD system, such as TMA and TEMAZ. However, compared to TEMAZ, we find the TMA surface treatment is effective to suppress the frequency dispersion and interface states in accumulation and depletion region. In order to further discuss the interface and gate oxide property of ZrO2/In0.53Ga0.47As MOSCAPs, we apply various post-deposition annealing temperatures with forming gas annealing (FGA). Moreover, by TMA pretreatment, we incorporate several Al2O3 inter-layers with the interface of ZrO2 and In0.53Ga0.47As and discuss their interface properties. It is noted that the MOSCAPs under PDA 300 °C with FGA show the best electrical characteristics at each Al2O3 inter-layer conditions. In addition, we utilize the conductance method to extract the density of interface states and still observe that the Dit exists near midgap is the lowest at PDA 300 °C with FGA. With the evidence of XPS analysis, we suppose that the result might be caused by higher amounts of the As2+/As2O5, As2O3/As2O5, and In2O3/InAsO4 at the MOSCAPs interface. Furthermore, from the electrical and interfacial chemistry characteristics, we demonstrate that the interface quality could be improved with thicker Al2O3 inter-layer. Eventually, we establish a distributed model to explain the tunneling mechanism between the semiconductor surface and trap states in the gate oxide which is biased in accumulation region. And we fit the experimental data with the model and quantitatively extract trap states density of the gate dielectric. As comparing with the aforementioned results, they are in good consistency.