利用蕭特基源極與汲極接面改善鍺通道金氧半場效電晶體之性能

Abstract

此論文中，首先我們分析金屬與鍺接面特性。將鎳金屬濺鍍在鍺基板上，討論在不同金屬沉積後退火溫度下產生的鎳鍺合金/鍺其二極體的電性與物性分析。在攝氏兩百度一分鐘氮氣內的條件下退火後的鎳鍺合金/n型二極體得到開關電流比有五個數量級；經由電流電壓方法(Current-Voltage method)可得到電子蕭特基能障(Schottky barrier for electron)為0.56電子伏特，理想因子(ideality factory)為1.07。由於費米能階釘札(Fermi-level pinning)靠近價帶(valance band)導致電洞蕭特基能障偏小且無法調節的現象，使得鎳鍺合金/p型二極體從實驗數據上可以得到一個歐姆接面特性；我們利用磷(Phosphorus)載子隔離(Dopant Segregation)的方式有效在鎳鍺合金/者接面建立較高的電洞蕭特基能障。本次實驗淬取出最大的開關電流比約四個數量級和電洞蕭特基能障為0.57電子伏特。利用三氧化二矽/二氧化鍺/鍺形成閘極介電層的鍺金氧半電容(MOSCAP)，搭配前述的實驗製作出金屬源極/汲極接面(Metal S/D)金氧半電晶體。並利用電導方法(conductance method)來萃取介面缺陷電荷密度，並發現介面缺陷電荷密度可經由300度30分鐘氫氣氮氣混合之熱退火可被降低；介面缺陷電荷密度的值在熱退火後下降了40%。而在熱退火後我們也發現了平帶電壓往正的方向移動以及較小的電壓遲滯現象。 其次，我們成功製作出鎳鍺合金的蕭特基n型金氧半電晶體；在光罩通道長度為10 m的元件擁有三個數量級的開關電流比和317 mV/dec的次臨界擺幅；接著利用攝氏300度30分鐘氫氣氮氣混合之熱退火可將特性改善為四個數量級的開關電流比和173 mV/dec的次臨界擺幅。在這元件中金屬源極/汲極接面有效的降低電阻值進而提高操作電流，相比傳統利用佈植製程的元件可有效從電阻方面改進。氫氣氮氣混合之熱退火可改善元件介面缺陷電荷密度和次臨界擺幅，但鎳鍺合金對於熱預算的要求是值得關切的。 最後，我們成功製作出鎳鍺合金的n型金氧半電晶體利用載子隔離，並比較和討論使用不同的載子活化溫度與載子佈植能量的元件特性；在攝氏500度一分鐘氮氣退火條件下光罩通道長度為10 m的n型元件擁有四個數量級的開關電流比和147 mV/dec的次臨界擺幅；不同佈植能量下我們猜測足夠情況下使用較低的能量可以減少損傷造成的漏電路徑，在活化足夠的情況下使用較低的退火溫度可以減少熱預算改善元件特性。

In this thesis, firstly, Ni/Ge junctions are formed by depositing Ni via sputtering and with different post metal annealing (PMA) temperatures. We electrically and physically analyze the NiGe/Ge junctions. The Ni/n-Ge contact with RTA at 200 °C has an effective electron barrier height (ΦBn) of 0.56 eV and an ideality factory of 1.07. Moreover, an Ion/Ioff ratio ~105 is obtained. It is obvious that for Ni/p-Ge the control sample without dopant segregation (DS) shows the ohmic contact behavior due to the strong Fermi level pinning (FLP) near the valence band and the resultant tiny ΦBp. The rectifying behavior is obtained by implanting phosphorus dopants into NiGe and the following RTA. Phosphorus atoms are supposed to segregate near at the NiGe/p-Ge interface through RTA. The extracted highest value of effective ΦBp is ~0.57 eV and an Ion/Ioff ratio ~3x104 is obtained. MOS capacitor of Al2O3/GeO2/p-Ge stack is fabricated and employed to examine the surface interface state density (Dit) near the midgap by conductance method at room temperature. Secondly, we investigate the effect of FGA on the metal-S/D PMOSFET characteristics. The on/off ratio of our NiGe/Ge junction and SB-PMOSFET (W/L = 100m/10m) reaches 3.5 and ~3 orders of magnitude, respectively. Better subthreshold swing (173mV/dec) can be obtained after FGA. For PMOSFETs, the on/off ratio of junction is improved using the metal source/drain, RTOTAL is decreased compared with that of the conventional PMOSFET. Pros and cons of FGA at 300 °C for 30 min on PMOSFET are summarized according to our experimental data. Positive VFB shift and subthreshold swing is obtained after FGA. However, the additional thermal budget may damage the NiGe junction because of the agglomeration of NiGe. Finally, we investigate the effect of dopant energy and drive-in annealing temperature on the characteristics of NiGe/Ge junction and device. The on/off ratio of our SB-NMOSFET (W/L = 100m/10m) is 2×104; subthreshold swing ~147mV/dec is obtained with an implant energy of 10 keV and a 400C drive-in annealing. For NMOSFETs, the on/off ratio of device is improved as the implant energy is reduced; RTOTAL of the NMOSFET subject to 500 C annealing is lower than that subject to 400 C annealing. Moreover, we show that the performance of NiGe Schottky S/D NMOSFET is more superior than that of the conventional device. Finally, our results exhibit high performance Ge NMOSFET with NiGe Schottky S/D has the potential for the future Ge MOSFET realization.