鍺環繞閘極奈米線金氧半場效電晶體及無接面電晶體、邏輯電路和靜態隨機存取記憶體之研究與分析

Abstract

本論文使用Technology Computer Aided Design (TCAD) 模擬器研究半導體材料鍺 (Ge) ，並對其特性作進一步分析。內容包含了兩個主題並如同下面的方式排列。第一部分研究單一電荷陷阱所導致的隨機電報雜訊 (Random Telegraph Noise, RTN) 對鍺奈米線電晶體 (Nanowire Transistor) 的元件特性、數位電路、與靜態隨機存取記憶體 (SRAM) 造成之影響，並將其與矽 (Si) 奈米線電晶體做比較。第二部分，我們研究鍺無接面電晶體 (Junctionless Transistor)，並提出增進其特性之方法。

在第一個研究中，由模擬結果可得知由於鍺材料之能帶穿隧機制，單一電荷陷阱所導致的隨機電報雜訊 (RTN) 對鍺與矽 (Si) 奈米線電晶體會有不同的影響。當單一電荷陷阱位於通道正中央時，隨機電報雜訊對矽奈米線電晶體的電流會有最嚴重的影響，而在鍺奈米線電晶體中，影響最嚴重的單一電荷陷阱位置則與電晶體之外加汲極電壓 (Vd) 有關。高汲極電壓操作下，鍺奈米線電晶體的關電流 (Ioff) 由通道靠近汲極端產生的穿隧電流主導，因此，單一電荷陷阱影響最嚴重之位置在通道靠近汲極區域。而在低汲極電壓操作下，由於穿隧效應減少，單一電荷陷阱影響最嚴重之位置與矽奈米線電晶體一樣在通道中央位置。

在第二個研究中，我們模擬兩種不同基板材料 (on Insulator 與on Si bulk substrate) 之鍺無接面電晶體。並分別提出對其使用雙重閘極功函數技術降低穿隧電流，以及使用高參雜濃度之矽基板降低關電流，來增進鍺無接面電晶體的開關電流比值 (Ion/Ioff) 、次臨界斜率 (Subthreshold Slope) 與增進其靜態隨機存取記憶體之讀寫靜態雜訊邊限(Read/ Write Static Noise Margin, RSNM/ WSNM)。

This thesis investigate and analysis the semiconductor material Germanium (Ge) using Technology Computer Aided Design (TCAD) simulator. It contains two topics and is organized as follows. In the first part, we investigate the impacts of a single trap induced Random Telegraph Noises (RTN) on Ge Nanowire (NW) MOSFETs, logic circuits and 6T Static Random Access Memory (SRAM), and compared it with its Silicon (Si) counterparts. In the second part, we investigate and analysis the Ge Junctionless Transistor and propose several techniques to improve its characteristic.

In the first work, the simulation results shows that due to the band-to-band tunneling (BTBT) mechanism of Ge, a single trap induced RTN shows different impacts on Ge-NW FET and Si-NW FET. The worst impact case of Si Nanowire Transistor is the condition with a single trap located in the middle region of channel. While for Ge-NW FET, the worst trap impact position depends on the supply drain bias Vd. Under high Vd condition, due to the off current (Ioff) of Ge NW is dominated by the band-to-band tunneling current which is generated in channel region near drain side, the worst trap impact position is the case with a single trap located near drain side. Under low Vd condition, band-to-band tunneling current decrease, thus Ge-NW FET shows similar impact s of trap position results to its Si counterpart under low drain bias.

In the second work, Ge Junctionless on Insulator and Ge Junctionless on Si bulk substrate are investigated. We proposed using dual work function technique and substrate doping design to these two structures respectively for reducing the Ioff. The result shows that, the on-off current (Ion/Ioff), subthreshold slope (S.S.) and Read/ Write Static Noise Margin (RSNM/ WSNM) are all improved using the techniques.